If you are designing digital circuits, debugging a microcontroller interface, or wiring up discrete logic gates, you need more than just abstract algebra. You need to know exactly which silicon to buy, what voltage it expects, and how it behaves under load. Boolean logic and truth tables form the theoretical foundation of digital electronics, mapping binary inputs (0 and 1) to deterministic outputs. But on the workbench, a "1" isn't just a concept—it's a specific voltage threshold, and a "0" is a current sink.

This reference guide bridges the gap between textbook theory and physical ICs. Below is the master lookup chart for standard logic gates, followed by the critical voltage and loading parameters that truth tables leave out.

The Master Boolean Logic and Truth Tables Reference Chart

How to read this table: The Gate and Expression columns define the mathematical operation. The 74HC (CMOS) and 74LS (TTL) columns provide the exact, industry-standard quad/dual DIP IC part numbers you will order from DigiKey or Mouser. The Truth Table Sequence lists the output states for inputs (00, 01, 10, 11). Standardized symbolic representations follow IEEE 315 / IEC 60617 conventions.

Standard Logic Gate IC Reference & Truth Table Outputs
Gate Type Boolean Expression 74HC Series (CMOS) 74LS Series (TTL) Truth Table Sequence (Out)
AND Y = A · B 74HC08 74LS08 0, 0, 0, 1
OR Y = A + B 74HC32 74LS32 0, 1, 1, 1
NAND Y = A · B 74HC00 74LS00 1, 1, 1, 0
NOR Y = A + B 74HC02 74LS02 1, 0, 0, 0
XOR Y = A ⊕ B 74HC86 74LS86 0, 1, 1, 0
NOT (Inverter) Y = A 74HC04 74LS04 1, 0 (Single Input)
Bench Tip: The NAND gate (74HC00) is considered a "universal gate." If you are stuck with only one IC type in your parts bin, you can wire multiple NAND gates together to create AND, OR, NOT, and XOR functions. This is exactly how early programmable logic arrays (PLAs) were architected.

Logic Families: Which Voltage Column Applies to Your Circuit?

A truth table tells you that an input of "1" yields an output of "1". It does not tell you that a "1" for a 74LS08 is anything above 2.0V, while a "1" for a 74HC08 running at 5V requires a minimum of 3.15V. Choosing the wrong logic family is the most common reason hobbyists fry microcontrollers or experience phantom switching.

Here is how to determine which voltage column and logic family applies to your installation:

  • 74HC (High-Speed CMOS): The modern default. Operates from 2.0V to 6.0V. If you are interfacing with a 5V Arduino Uno, or dropping down to 3.3V for an ESP32 or Raspberry Pi Pico, 74HC is your baseline. It features high input impedance (draws almost zero current at the gate) and symmetrical drive strength.
  • 74LS (Low-Power Schottky TTL): Legacy bipolar technology. Strictly a 5V family (4.75V to 5.25V). It requires significant input current to pull a pin LOW. Never use 74LS to drive 3.3V microcontroller inputs directly; the HIGH output voltage ($V_{OH}$) of a 74LS gate is only guaranteed to be 2.7V minimum, which can cause brownouts or undefined states on modern 3.3V silicon.
  • CD4000 Series (Standard CMOS): The original 4000-series CMOS. Great for high-voltage, low-speed applications (up to 15V or 18V), such as driving relays in 12V automotive or solar control circuits. Too slow for high-speed data buses.

For a deep dive into the exact input/output voltage thresholds ($V_{IH}$, $V_{IL}$, $V_{OH}$, $V_{OL}$) across different supply voltages, always consult the manufacturer's specific datasheet, such as the Texas Instruments SN74HC00 Datasheet. The All About Circuits digital textbook also provides excellent foundational theory on how these thresholds are derived from the underlying transistor physics.

Fan-Out Derating and Loading: Modifying the Base Value

In wire sizing, derating reduces ampacity based on heat and bundling. In digital logic, fan-out derating modifies the base drive capability of a gate based on the electrical load of the inputs it is trying to drive. A truth table assumes an ideal, infinite-impedance load. Physical silicon does not.

Fan-out is the maximum number of gate inputs a single gate output can reliably drive without the voltage dropping out of spec.

  • HC driving HC: Because CMOS inputs are essentially tiny capacitors (around 3pF to 10pF) with near-infinite DC resistance, a single 74HC output can theoretically drive 50+ HC inputs. The DC fan-out is massive.
  • HC driving LS: Here, derating hits hard. A 74LS input requires up to 0.4mA of current to pull LOW. A 74HC output can only sink about 4mA to 6mA safely while maintaining a valid logic "0" voltage. Therefore, the fan-out of an HC gate driving LS inputs is derated to roughly 10 to 15.
  • Capacitive Loading Derating: Every time you add an input, a PCB trace, or a breadboard wire, you add parasitic capacitance. As a rule of thumb for 74HC logic at 5V, every 15pF of additional load capacitance adds roughly 1ns to 1.5ns of propagation delay. If you fan-out a clock signal to 20 gates on a breadboard, your clean 10MHz square wave will degrade into a slow, rounded triangle wave, causing double-clocking and system crashes.
The Fix: If your calculated fan-out exceeds the gate's derated limit, or if you are driving a long, capacitive cable, insert a buffer IC (like the 74HC244 octal buffer). Buffers are designed with heavier output transistors specifically to handle high capacitive loads without degrading the signal edges.

What the Truth Table Cannot Tell You: Timing and Glitches

The most dangerous assumption a beginner makes is that boolean logic happens instantaneously. A truth table is a static map; it cannot tell you about propagation delay ($t_{pd}$), setup times, or transient glitches.

When an input changes state, the internal transistors take time to charge and discharge. For a standard 74HC00 at 5V, this propagation delay is typically 8 to 12 nanoseconds. In simple LED blinking, this is irrelevant. In high-speed SPI buses or state machines, it is everything.

The Race Condition Hazard: Consider an XOR gate (74HC86) where both inputs transition simultaneously from (0,1) to (1,0). The truth table says the output should remain "1". However, internally, the signal path for one input might be 2ns faster than the other. For a brief 2ns window, the internal logic might see a (0,0) or (1,1) state, causing the output to momentarily spike to "0" before settling back to "1". This is known as a glitch or hazard.

If that XOR output is connected to the clock pin of a flip-flop or a counter, that 2ns glitch will be interpreted as a valid clock edge, advancing your counter prematurely and destroying your data integrity. Truth tables will not warn you about this. To catch it, you must look at the timing diagrams in the datasheet and design your circuit using synchronous clocking (D-flip flops) rather than relying on asynchronous combinatorial logic for state changes.