Boolean Logic Symbols Reference Chart: ANSI vs IEC Gate Shapes

When reading schematics or tracing printed circuit boards (PCBs), misidentifying a single logic gate can send your debugging process down a multi-hour rabbit hole. The physical shape of a gate on a drawing depends entirely on the drafting standard the engineer used, but the underlying boolean math remains identical. Below is the direct translation between the two dominant global standards.

The Complete Boolean Logic Symbols Reference Table

This table maps the seven fundamental boolean gates across the US-centric shaped standard and the international rectangular standard. Use this as your primary bench reference when cross-referencing datasheets with schematic drawings.

Regional Standards: ANSI/IEEE vs. IEC 60617 vs. DIN

The symbol you encounter on a schematic is dictated by the region and the era of the design. Understanding which standard applies to your reader's region prevents critical misinterpretations.

ANSI/IEEE Std 91 (United States & Legacy Military)

The ANSI/IEEE standard uses distinct geometric shapes for each gate. This is the default in North America, heavily used in US military documentation, and universally taught in American university engineering programs. The shapes are highly intuitive once learned—the D-shape for AND and the shield-shape for OR are visually distinct even on poorly printed schematics. According to All About Circuits, this shaped notation remains the dominant language for hobbyists and US-based commercial hardware designers.

IEC 60617-12 (Europe, International & Modern CAD)

The International Electrotechnical Commission (IEC) standard abandons unique outer shapes in favor of uniform rectangular boxes. The logic function is indicated by an internal alphanumeric qualifier. This standard is mandatory for most European industrial documentation and is increasingly common in modern CAD tools globally because rectangular boxes route orthogonal wires much cleaner on dense, multi-layer PCB schematics.

DIN 40700 (Legacy German)

You will occasionally encounter DIN symbols on older European equipment (pre-1990s). DIN used semi-rectangular shapes with internal numeric codes (e.g., a rectangle with a curved right edge for AND). DIN was officially superseded by IEC 60617, but maintenance technicians working on legacy German industrial PLCs or CNC machines still need to recognize them.

The "Rows People Get Wrong" & Faded Silkscreen Troubleshooting

Rows People Get Wrong

• XOR vs. XNOR in IEC: The most common misread in the IEC standard is confusing the OR gate (≥1) with the XOR gate (=1). If the inputs are A and B, ≥1 means "one OR MORE inputs are high" (standard OR). =1 means "EXACTLY ONE input is high" (XOR). Missing that single equals sign changes your entire truth table.
• De Morgan's Equivalents (Negative Logic): A NAND gate (AND with a bubble on the output) is logically identical to a Negative-OR gate (OR with bubbles on the inputs). Schematics often draw a NAND gate with input bubbles and an OR shape to indicate that the signal is active-low. If you see an OR shape with bubbles on the inputs and no bubble on the output, it is physically a NAND gate (like a 74HC00), not an OR gate.
• The Buffer vs. NOT Gate: A buffer is drawn as a triangle (ANSI) or a rectangle with 1 (IEC) but lacks the inversion bubble. It does not change the logic state; it only provides current amplification or signal isolation.

Safe Interpretation When Markings Are Faded or Missing

When repairing industrial control boards or vintage synthesizers, heat and conformal coating often destroy the PCB silkscreen, leaving you with unmarked 14-pin SOIC or DIP chips. Here is the bench procedure to identify the logic gate safely:

1. Identify Power Pins: For standard 14-pin 74-series and 4000-series logic ICs, Pin 14 is VCC (connect to 5V for 74HC, or 3.3V/5V depending on the specific sub-family) and Pin 7 is GND. For 4000-series CMOS, VCC can be up to 15V, so verify the voltage rail with a multimeter before applying power.
2. Map the Pins: Logic gates in a 14-pin package are usually arranged as four 2-input gates (e.g., 74HC00). The pinout typically follows the pattern: [Input A, Input B, Output] for gates 1, 2, and 3, with the fourth gate mirrored at the bottom of the chip.
3. Truth Table Probing: Power the board. Use a logic probe or a multimeter set to DC voltage. If Pins 1 and 2 read HIGH (near VCC) and Pin 3 reads LOW (near GND), you are looking at a NAND gate. If Pin 3 reads HIGH when both inputs are HIGH, it is an AND gate.
4. Diode Test Fallback: If the board is completely dead and unpowered, set your multimeter to diode test mode. Measure between the suspected input pins and VCC/GND. CMOS inputs have internal protection diodes. You will read a ~0.6V drop from Input to VCC (reverse biased in circuit, forward biased by meter) which helps confirm which pins are inputs versus outputs.

Boolean Logic Symbols FAQ

What is the difference between positive and negative logic symbols?

Positive logic assumes a HIGH voltage (e.g., 5V) represents a logical '1' (True) and LOW voltage (0V) represents a logical '0' (False). Negative logic reverses this: LOW voltage is '1' and HIGH is '0'. In schematic symbols, negative logic is indicated by "assertion-level" bubbles. A bubble on an input pin means the gate triggers when that pin goes LOW. A bubble on an output pin means the output actively pulls LOW when the condition is met. This is common in reset lines and chip-enable pins.

How do I read a buffer symbol versus a NOT gate?

In the ANSI standard, both look like triangles pointing to the right. The NOT gate (inverter) has a small circle (bubble) at the tip of the triangle. The buffer has no bubble. In the IEC standard, both are rectangles. The NOT gate has a 1 inside with a bubble on the output line. The buffer has a 1 inside with no bubble. Buffers are used to drive high-current loads (like relays or LEDs) or to clean up degraded signals over long traces, without altering the boolean state.

Why do some schematics use a dot for an AND gate instead of a shape?

In mathematical boolean algebra and high-level block diagrams, the AND operation is represented by a dot (A · B) or simply by placing variables next to each other (AB). The OR operation uses a plus sign (A + B). You will see this notation in FPGA hardware description languages (like Verilog or VHDL) documentation, state-machine flowcharts, and academic papers where drawing full gate shapes would clutter the diagram. The dot strictly means logical multiplication (AND), never a physical wire junction.