An XNOR gate outputs a logical HIGH (1) only when all its inputs share the exact same logic state, functioning fundamentally as a digital equality detector. In a real circuit, swapping an XOR for an XNOR changes a difference-detector into a match-detector, completely reversing the routing logic in parity checkers and digital comparators. Beginners frequently confuse the XNOR gate with a standard NOR gate; remember that a NOR gate requires all inputs to be LOW to output HIGH, whereas an XNOR outputs HIGH when inputs are both HIGH or both LOW. Understanding the boolean expression for XNOR gate logic is critical when designing equivalence checkers, phase-locked loops, and error-correcting memory arrays.
The Boolean Expression for XNOR Gate and Truth Table
The mathematical foundation of this gate is an inverted exclusive-OR operation. The standard boolean expression for XNOR gate logic with two inputs (A and B) is written as:
Y = \overline{A \oplus B} or Y = AB + \overline{A}\overline{B}
Read as: Y equals A XNOR B, or Y equals (A AND B) OR (NOT A AND NOT B).
While the abstract math is straightforward, bench work requires translating these logic states into physical voltages. Below is the truth table mapped directly to the real-world electrical characteristics of a standard 5V CMOS IC (like the Texas Instruments SN74HC266). Notice that logic levels are not perfect 0V and 5V; they operate within guaranteed threshold windows.
| Input A (Logic) | Input B (Logic) | Output Y (Logic) | Typical V_in (Volts) | Guaranteed V_out (Volts) |
|---|---|---|---|---|
| 0 (LOW) | 0 (LOW) | 1 (HIGH) | 0.0V - 1.5V (V_IL) | Min 4.5V (V_OH) |
| 0 (LOW) | 1 (HIGH) | 0 (LOW) | Mixed | Max 0.5V (V_OL) |
| 1 (HIGH) | 0 (LOW) | 0 (LOW) | Mixed | Max 0.5V (V_OL) |
| 1 (HIGH) | 1 (HIGH) | 1 (HIGH) | 3.5V - 5.0V (V_IH) | Min 4.5V (V_OH) |
Critical Bench Note: For 5V HC-series CMOS, the minimum voltage guaranteed to register as a HIGH input (V_IH) is 3.5V. If you attempt to drive a 5V XNOR gate directly from a 3.3V microcontroller GPIO, the 3.3V signal falls below the 3.5V threshold, resulting in an indeterminate state or excessive shoot-through current. You must use a level shifter or run the XNOR IC at 3.3V VCC.
Worked Numeric Example: Building a 4-Bit Equivalence Checker
Let’s apply the boolean expression for XNOR gate logic to a practical scenario: verifying if two 4-bit binary words are identical. We will use four individual 2-input XNOR gates (one from a 74HC266 quad IC) and feed their outputs into a 4-input AND gate (74HC21).
- Bit 0 (LSB): A=1, B=1 → XNOR outputs 1.
- Bit 1: A=1, B=1 → XNOR outputs 1.
- Bit 2: A=0, B=0 → XNOR outputs 1.
- Bit 3 (MSB): A=1, B=1 → XNOR outputs 1.
The AND gate receives 1111 and outputs a final HIGH, confirming a match. If even one bit differs (e.g., Word B = 1001), Bit 2’s XNOR gate receives 0 and 1, outputting a 0. The AND gate immediately pulls the final output LOW.
Calculating Propagation Delay and Power
In high-speed digital designs, logic levels are only half the battle; timing is the other. According to the digital logic principles outlined by All About Circuits, cascading gates introduces cumulative latency.
- Gate Delay (t_pd): A 74HC266 at 5V with a 15pF capacitive load has a maximum propagation delay of 18ns per gate.
- AND Gate Delay: The 74HC21 4-input AND gate adds another 15ns of delay.
- Total Worst-Case Latency: 18ns (XNOR stage) + 15ns (AND stage) = 33ns.
If your system clock runs at 50MHz (20ns period), this 33ns combinational path will cause a setup-time violation. You would need to pipeline the comparison or drop to a faster logic family, such as 74LVC or 74AC series, which can push delays below 5ns.
Where You Meet XNOR Logic in Practice
You won't often see a standalone XNOR gate on a modern PCB, but the boolean expression for XNOR gate logic is heavily embedded inside larger silicon architectures.
1. Parity Generators and Checkers (ECC RAM)
In computer memory, Error-Correcting Code (ECC) RAM uses trees of XOR and XNOR gates to generate and verify parity bits. When a 64-bit word is written to memory, an XNOR tree calculates the expected parity. On read, the same tree recalculates it. If the stored parity and calculated parity mismatch, the XNOR output flips, triggering the memory controller to correct single-bit errors via the Hamming code algorithm.
2. Phase Detectors in Phase-Locked Loops (PLLs)
In analog-mixed-signal ICs like the classic CD4046 PLL, Phase Comparator I is essentially an XNOR gate. When comparing the phase of a reference oscillator to a Voltage-Controlled Oscillator (VCO), the XNOR gate outputs a HIGH pulse whenever both signals match. If the frequencies are identical and perfectly in phase, the XNOR output stays solidly HIGH. If they drift out of phase, the output becomes a PWM square wave. A low-pass filter smooths this PWM into a DC control voltage that steers the VCO back into lock.
3. Digital Magnitude Comparators
Inside a 74HC85 4-bit magnitude comparator, XNOR gates act as the frontline equivalence checkers. Before the chip decides if A > B or A < B, it uses internal XNOR logic to mask out the bits that are identical, allowing the cascading logic to focus strictly on the most significant bit where a difference actually exists.
Common Pitfalls and IC Selection: The Open-Drain Trap
The most common mistake hobbyists and junior engineers make when ordering XNOR logic ICs is ignoring the output stage topology. Not all XNOR gates are created equal.
Bench Warning: The 74HC266 Open-Drain Gotcha
The standard 74HC266 Quad 2-Input XNOR gate features open-drain outputs. It can pull the output line to ground (LOW), but it cannot drive it HIGH. If you wire a 74HC266 directly to an LED or a microcontroller input without a pull-up resistor (typically 4.7kΩ to 10kΩ to VCC), the HIGH state will float, resulting in erratic switching and susceptibility to EMI.
Why did manufacturers design it this way? Open-drain outputs allow you to wire multiple XNOR gates together in a 'wire-OR' configuration to build massive parity trees without using additional AND/OR gates. However, for standard point-to-point logic, it is a nuisance.
The Solution: If you need a standard push-pull XNOR gate that drives HIGH and LOW natively without pull-up resistors, specify the 74HC7266 or the older CD4077 (if using 4000-series CMOS). Always check the datasheet's output stage schematic before finalizing your bill of materials.
Frequently Asked Questions
Can I build an XNOR gate using only NAND gates?
Yes. Because NAND gates are universal, you can construct the boolean expression for XNOR gate logic using exactly five NAND gates. You generate the inverted and non-inverted signals, combine them through two intermediate NAND gates to simulate the AND operations, and feed those into a final NAND gate acting as the OR/invert stage. This is common in FPGA fabric where NAND/NOR primitives are the base logic elements.
What happens if I leave one input of an XNOR gate floating?
In CMOS logic (like 74HC or CD4000 series), a floating input acts as an antenna, picking up ambient electromagnetic noise. The gate will oscillate wildly between HIGH and LOW, causing massive internal shoot-through current that can overheat and destroy the IC. Always tie unused inputs to VCC or GND via a 10kΩ resistor, or directly if the specific datasheet permits.
Is XNOR the same as an equivalence gate?
For 2-input gates, yes; XNOR and Equivalence are functionally identical. However, for 3 or more inputs, the terminology diverges. A 3-input XNOR is typically an XOR gate followed by an inverter. A 3-input Equivalence gate outputs HIGH only if all three inputs are identical (000 or 111). Always verify the specific boolean expression in the manufacturer's datasheet when dealing with gates beyond two inputs.
