A boolean equation truth table is the foundational blueprint of digital electronics. It maps every possible combination of binary inputs to a single, deterministic output, governed by a specific Boolean algebra expression. Whether you are debugging a stuck GPIO pin on an ESP32, designing a custom state machine with 74HC-series logic chips, or simplifying a Karnaugh map for an FPGA, the truth table is your ultimate source of truth. However, reading an abstract table on a chalkboard is very different from applying it to physical silicon operating at 3.3V or 5.0V.
This reference guide bridges the gap between abstract Boolean math and physical bench work. Below, you will find the master reference chart based on IEEE Std 91/91a standards for logic functions, followed by critical guidance on how physical operating conditions and timing constraints modify these ideal mathematical states.
The Master Boolean Equation Truth Table Reference
The following table outlines the standard 2-input logic gates. This data conforms to the symbolic and functional standards set by IEEE Std 91 and matches the functional behavior of standard CMOS families like the 74HC and CD4000 series.
| Gate Type | Boolean Equation | Inputs (A, B) | Output (Y) | Standard CMOS IC |
|---|---|---|---|---|
| AND | Y = A · B | 00, 01, 10, 11 | 0, 0, 0, 1 | 74HC08 / CD4081 |
| OR | Y = A + B | 00, 01, 10, 11 | 0, 1, 1, 1 | 74HC32 / CD4071 |
| XOR | Y = A ⊕ B | 00, 01, 10, 11 | 0, 1, 1, 0 | 74HC86 / CD4030 |
| NAND | Y = $\overline{A \cdot B}$ | 00, 01, 10, 11 | 1, 1, 1, 0 | 74HC00 / CD4011 |
| NOR | Y = $\overline{A + B}$ | 00, 01, 10, 11 | 1, 0, 0, 0 | 74HC02 / CD4001 |
Applying the Table: Active States, Modifiers, and Timing
A theoretical boolean equation truth table assumes instantaneous transitions and perfect voltage levels. Physical installations require you to account for active states, logic simplification modifiers, and timing constraints.
Which Output Column Applies to Your Installation?
When working with sequential logic (like the 74HC74 D-type flip-flop) or drivers (like the 74HC240 buffer), the truth table will often feature two output columns: $Q$ (non-inverted) and $\overline{Q}$ (inverted). Which column applies to your specific installation depends entirely on your downstream load.
- Use the $Q$ (Active-High) column when driving NPN transistor bases, enabling high-side P-channel MOSFETs, or feeding data into a microcontroller GPIO configured with internal pull-down resistors.
- Use the $\overline{Q}$ (Active-Low) column when sinking current through an LED to ground, driving relay coils on the low side, or triggering interrupt pins on an ESP32 that are configured to fire on a falling edge.
How "Derating" Rows (Don't Care Conditions) Modify the Base Value
In electrical wiring, derating rows reduce a wire's base ampacity based on temperature. In digital logic truth tables, the equivalent concept is the "Don't Care" (X) condition. When a specific combination of inputs can never physically occur in your circuit (for example, inputs 10 and 11 on a BCD-to-decimal decoder, since binary 1010 through 1111 are invalid in BCD), the truth table marks the output as 'X'.
These 'X' rows modify the base boolean equation by allowing the designer to assign them a value of either 0 or 1—whichever results in the simplest possible logic expression when plotted on a Karnaugh map. Additionally, physical temperature derating applies to the voltage thresholds: as ambient temperature rises above 25°C, the $V_{IH}$ (minimum voltage to register a '1') of a CMOS gate slightly decreases, meaning a noisy 2.8V signal that registered as a '0' at room temperature might accidentally cross the threshold and register as a '1' in a hot enclosure.
What the Boolean Equation Truth Table Cannot Tell You
The most common mistake hobbyists make is assuming the truth table represents the complete behavior of the IC. The truth table only shows steady-state DC logic. It cannot tell you:
- Propagation Delay ($t_{pd}$): The output does not change the exact nanosecond the input changes. A 74HC08 at 5V has a typical $t_{pd}$ of 18ns. If your inputs change simultaneously, slight mismatches in internal gate delays can cause a momentary "glitch" or false pulse on the output.
- Setup and Hold Times: For flip-flops and latches, the data input must be stable for a specific number of nanoseconds before and after the clock edge. Violating this causes metastability, where the output oscillates or settles at an invalid voltage level.
- Fan-out Limits: The table tells you what voltage the output produces, but not how much current it can source or sink. A standard 74HC output can only safely drive about 4mA to 6mA per pin.
FAQ: Common Boolean Equation Truth Table Questions
How do I convert a boolean equation truth table into a physical logic circuit?
Start by identifying the rows in the truth table where the output is '1'. Write a minterm (AND expression) for each of those rows. For example, if the output is '1' only when A=1 and B=0, the minterm is $A \cdot \overline{B}$. Combine all minterms with OR gates to create a Sum of Products (SOP) equation. Finally, map that equation to physical ICs: use a 74HC04 for the inverters, a 74HC08 for the AND gates, and a 74HC32 for the OR gates. For complex tables, use a Karnaugh map to simplify the equation before buying parts, which reduces your IC count and propagation delay.
Why does my boolean equation truth table show 'X' or 'Z' states?
An 'X' (Don't Care) state means the input combination is either impossible in normal operation or the output state is irrelevant to the system's function; designers use 'X' to optimize and simplify the final boolean equation. A 'Z' (High-Impedance) state appears in truth tables for tri-state buffers (like the 74HC125) or bus transceivers. When the enable pin is inactive, the output physically disconnects from the internal circuitry, presenting an extremely high resistance (often >100 MΩ) to the external circuit. This allows multiple ICs to share the same data bus without short-circuiting each other.
What is the difference between a truth table and a state table?
A standard boolean equation truth table is used for combinational logic (like AND/OR gates), where the output depends solely on the present inputs. A state table (or state transition table) is used for sequential logic (like flip-flops, counters, and shift registers). A state table includes not only the current inputs and current state, but also the next state and the clock edge condition. If your circuit has memory or relies on a clock signal, you must use a state table rather than a basic combinational truth table.
Can I use NAND gates to build any truth table?
Yes. NAND gates are "universal gates." You can construct any boolean equation truth table using only 74HC00 NAND ICs. By tying both inputs of a NAND gate together, it acts as a NOT gate (inverter). By cascading NAND gates, you can build AND, OR, and XOR functions. While this is a classic computer science exercise, in practical bench work, it is usually better to use the specific IC for the job (e.g., using a dedicated 74HC86 XOR chip) to minimize chip count, reduce board space, and lower cumulative propagation delay.
