Applying the Boolean Distributive Law in PLC and FPGA Logic Design

The Boolean distributive law states that a logical variable can be multiplied (ANDed) or added (ORed) across a grouped expression without changing the final logical output. When you are programming a Siemens S7-1200 PLC, designing hardwired relay panels, or routing logic on an AMD/Xilinx FPGA, this isn't just abstract math—it is the primary mechanism for reducing gate count, cutting propagation delay, and shrinking PLC scan times. By factoring out common variables, engineers routinely shrink 6-gate circuits down to 3 gates, saving silicon area, lowering power consumption, and reducing hardware costs.

The Two Forms of the Boolean Distributive Law

The first form—ANDing a variable across an OR group—behaves exactly like standard arithmetic. If you have a main enable switch (A) that must be ON alongside either a forward limit (B) or a reverse limit (C), you can write it as A · (B + C) or expand it to (A · B) + (A · C). Both yield the exact same truth table.

The second form—ORing a variable across an AND group—is where digital logic diverges from standard math. In regular arithmetic, 2 + (3 × 4) equals 14, but (2 + 3) × (2 + 4) equals 30. In Boolean algebra, however, A + (B · C) is perfectly equivalent to (A + B) · (A + C). This works because Boolean variables are capped at a maximum value of 1, and the system relies on the idempotent law (A · A = A and A + A = A), which prevents the exponential growth seen in standard arithmetic. For a deeper mathematical proof of these identities, refer to the Boolean algebraic identities chapter in standard digital electronics texts.

Worked Numeric Example: Optimizing a Motor Control Interlock

Let's look at a real-world scenario where expanding or factoring an expression changes the physical hardware required. Suppose we are designing a safety interlock for a conveyor motor. The motor (M) runs if the Main Enable (E) is HIGH, AND either Sensor A (A) OR Sensor B (B) is HIGH.

Expanded Form: M = (E · A) + (E · B)
Factored Form: M = E · (A + B)

Let's evaluate both forms using a specific numeric state: E = 1 (Enabled), A = 0 (Sensor A blocked), B = 1 (Sensor B clear).

Evaluation Step	Expanded: (E · A) + (E · B)	Factored: E · (A + B)
Substitute Values	(1 · 0) + (1 · 1)	1 · (0 + 1)
Resolve Inner Groups	0 + 1	1 · 1
Final Output	1 (Motor Runs)	1 (Motor Runs)
Hardware Required	Two AND gates, One OR gate (3 total)	One OR gate, One AND gate (2 total)

While the logical output is identical, the physical implementation is vastly different. The expanded form requires three logic gates. The factored form requires only 2 gates. In a Xilinx Artix-7 FPGA, a 3-gate implementation might consume two separate 6-input LUTs (Look-Up Tables) due to routing constraints, while the 2-gate version packs cleanly into a single LUT. This reduces silicon area and cuts the dynamic power draw of that logic block by roughly 15%. For hardwired relay logic, factoring out the common variable E means you buy and wire one main relay contact instead of two, saving approximately $40 in hardware and an hour of panel wiring time.

Where You Meet This in Practice

You will rarely sit down with a pen and paper to apply the distributive law manually in modern engineering, but you will interact with its results constantly across three domains:

• PLC Ladder Logic (IEC 61131-3): When you draw a branch in a PLC ladder diagram that shares a common input instruction (like an XIC - Examine If Closed), the PLC compiler uses the distributive law to optimize the underlying bytecode. Factoring out common contacts reduces the instruction count, directly decreasing the PLC scan cycle time by microseconds per rung—a critical metric in high-speed packaging machines.
• FPGA/CPLD Synthesis: Synthesis tools like AMD Vivado or Intel Quartus automatically apply the distributive law (along with other Boolean theorems) during the "Logic Optimization" phase. They factor expressions to fit logic into the smallest possible number of LUTs, minimizing propagation delay and preventing timing violations on high-speed clock domains.
• Hardwired Relay and Contactor Panels: In industrial motor control centers, physical space on the DIN rail is at a premium. Applying the distributive law to your schematic allows you to place a master safety relay contact on the trunk line of a circuit, rather than duplicating that contact across every parallel motor starter branch. This is detailed further in practical circuit simplification examples for relay logic.

Common Confusions: Distributive vs. Absorption vs. De Morgan's

When troubleshooting or optimizing logic, engineers frequently confuse the distributive law with two other fundamental Boolean rules. Knowing the difference prevents catastrophic logic errors in safety circuits.

The Absorption Law (A + (A · B) = A): People often try to apply the distributive law to expressions where a variable is repeated, resulting in messy expansions. The absorption law simply dictates that if a variable is OR'd with its own AND'd product, the product term is redundant and gets absorbed. If A is true, the whole expression is true regardless of B.

De Morgan's Laws (NOT(A · B) = NOT(A) + NOT(B)): The distributive law does not handle inversions (NOT gates) over groups. If you have a NAND or NOR gate feeding a grouped expression, you must apply De Morgan's theorem first to break the inversion bar before you can apply the distributive law to the underlying variables.

Standard Arithmetic Limits: As mentioned, trying to apply the OR-over-AND form (A + BC = (A+B)(A+C)) to standard numbers will yield incorrect results. This rule exists strictly because binary logic operates on a closed set of {0, 1} where 1 + 1 = 1, not 2.