Binary symbols are the standardized graphical representations of Boolean logic operations in digital schematics. If you are reading a schematic printed in North America, you will almost exclusively see ANSI/IEEE Std 91 distinctive shapes. If you are reading a European schematic, an IEC military spec, or a modern FPGA vendor datasheet, you will encounter IEC 60617-12 rectangular outlines. Knowing both is mandatory for bench troubleshooting and cross-border design reviews.
The Complete Binary Logic Symbol Reference Table
The table below maps the core binary logic gates across both dominant standards, including their Boolean equivalents and the most common 74-series HC (High-Speed CMOS) and LS (Low-Power Schottky) IC part numbers you will find on a workbench.
| Gate Type | Boolean Function | ANSI/IEEE Std 91 (US Distinctive) | IEC 60617-12 (EU Rectangular) | Common IC (DIP-14) |
|---|---|---|---|---|
| AND | A · B | D-shape (flat back, curved front) | Rectangle with & qualifier |
74HC08 / 74LS08 |
| OR | A + B | Curved back, pointed front | Rectangle with ≥1 qualifier |
74HC32 / 74LS32 |
| NOT | A' | Triangle with output bubble | Rectangle with 1 and right-edge bubble |
74HC04 / 74LS04 |
| NAND | (A · B)' | D-shape with output bubble | Rectangle with & and right-edge bubble |
74HC00 / 74LS00 |
| NOR | (A + B)' | Curved OR shape with output bubble | Rectangle with ≥1 and right-edge bubble |
74HC02 / 74LS02 |
| XOR | A ⊕ B | OR shape with extra curved input line | Rectangle with =1 qualifier |
74HC86 / 74LS86 |
| XNOR | (A ⊕ B)' | XOR shape with output bubble | Rectangle with =1 and right-edge bubble |
74HC266 / 74LS266 |
For a deeper dive into how these gates are constructed at the transistor level, the All About Circuits digital logic textbook provides excellent CMOS and TTL internal schematics.
Regional Standards and the "Rows People Get Wrong"
The transition between ANSI and IEC symbols trips up many hobbyists and junior engineers. ANSI relies on the physical shape of the symbol to convey meaning, while IEC uses a uniform rectangular box and relies on internal alphanumeric qualifiers (dependency notation) to define the logic.
The Rows People Get Wrong
- The XOR/XNOR Bubble Trap: In ANSI schematics, the extra curved line on the input side of an XOR gate is not an inversion bubble. It is merely a shape identifier. However, designers sometimes place an inversion bubble on the input of an XOR gate to indicate an active-low enable. Logically, an XOR with an inverted input behaves identically to an XNOR, but schematically, it implies a different physical intent (e.g., triggering on a falling edge). Always check which side of the gate the bubble sits on.
- Misreading IEC Qualifiers: The IEC
≥1symbol inside a rectangle means "if one or more inputs are high, the output is high" (an OR gate). Beginners often misread this as a mathematical comparator. Similarly,&means "all inputs must be high" (AND), and=1means "exactly one input must be high" (XOR). - Active-Low Bubbles on IEC Rectangles: In IEC 60617, a bubble (negation indicator) can be placed on the input or output edges of the rectangle. A bubble on the left edge means the input is active-low. A bubble on the right edge means the output is active-low. Do not confuse an input bubble with an output bubble; they fundamentally change how you wire the microcontroller GPIO to that pin.
When replacing a faded 74-series IC based on its binary symbol function, do not blindly swap a 74LS (TTL, 5V nominal) with a 74HC (CMOS, 2V-6V) without checking the surrounding circuit. While the binary logic symbol on the schematic remains identical, a 74HC chip driven by a 3.3V microcontroller will work perfectly, whereas a 74LS chip will fail to register a 3.3V signal as a logic HIGH (it requires ~2.0V minimum, but noise margins are razor-thin at 3.3V). Always match the logic family to the bus voltage.
Safe Interpretation When Silkscreen Markings Are Faded or Missing
On the repair bench, you will frequently encounter industrial control boards or vintage audio gear where the IC silkscreen is rubbed off, laser-etched poorly, or obscured by conformal coating. If you know the binary symbol function required by the circuit but need to identify the exact silicon, follow this diagnostic path.
- Locate VCC and GND: For standard 14-pin DIP logic ICs, Pin 14 is VCC and Pin 7 is GND. (For 16-pin, it is Pin 16 and Pin 8). Verify this with a multimeter in continuity mode against a known chassis ground or bulk capacitor negative terminal.
- Identify the Gate Topology: Power the board. Use a logic probe or an oscilloscope on the suspected output pin (e.g., Pin 3). Force the corresponding input pins (Pins 1 and 2) low using a 1kΩ pulldown resistor to ground. If the output goes HIGH, you are looking at a NAND gate. If the output stays LOW, it is a NOR gate.
- Determine the Logic Family: Measure the voltage on the VCC pin. If it reads exactly 5.0V, it is likely a legacy TTL (74LS) or standard CMOS (74HC) family. If it reads 3.3V, it is almost certainly a modern LVC or LVX family (e.g., 74LVC00).
Never force a CMOS binary logic output HIGH or LOW by shorting it directly to VCC or GND with a jumper wire to test its state. Modern CMOS outputs (like the 74HC series) can source or sink up to 25mA per pin. Shorting a HIGH output to GND will instantly exceed the absolute maximum ratings, melting the internal silicon and permanently bricking the IC. Always use a logic pulser, a high-impedance oscilloscope probe, or a resistor (≥470Ω) to safely manipulate nodes.
For comprehensive cross-referencing of logic families and their electrical characteristics, the Texas Instruments Logic Portal maintains up-to-date selection guides detailing the exact voltage thresholds and propagation delays for every modern binary logic family.
Frequently Asked Questions
What is the difference between positive and negative logic binary symbols?
Positive logic assigns a HIGH voltage (e.g., 5V or 3.3V) to a binary '1' and LOW (0V) to a binary '0'. Negative logic inverts this: a LOW voltage represents a binary '1' (asserted state), and HIGH represents a binary '0'. In schematics, negative logic is denoted by placing inversion bubbles on the inputs or outputs of the binary symbols. An AND gate with negative-logic inputs and a positive-logic output behaves identically to a positive-logic NOR gate. Designers use negative logic symbols to make the schematic match the physical intent of active-low control signals, like a microcontroller's active-low RESET or CHIP_SELECT lines.
Why do some binary symbols use a triangle with a circle instead of a D-shape?
A triangle is the universal ANSI/IEEE symbol for a non-inverting buffer or driver, while a triangle with a circle (bubble) on the output is an inverter (NOT gate). You will sometimes see a triangle used where you expect a D-shape (AND) or curved shape (OR) when the IC is being used purely as a buffer to increase current drive capability, rather than to perform multi-input Boolean math. For example, tying both inputs of a 74HC00 NAND gate together turns it into a NOT gate; on a schematic, a designer might draw it as a triangle with a bubble to clarify its function as an inverter, even if the physical chip is a NAND IC.
How do I read IEC 60617 dependency notation on complex binary symbols like flip-flops?
While simple gates use & or ≥1, complex binary symbols like D-flip-flops and latches use IEC dependency notation to show how inputs interact. For example, a letter like C followed by a number (e.g., C1) indicates a control dependency. If a clock input is labeled C1, and a data input is labeled 1D, the "1" links them: the D input is only acted upon when the C1 (clock) condition is met. An R indicates a reset dependency, and an S indicates a set dependency. If an R input has a bubble, it is an active-low asynchronous reset. Mastering this notation allows you to read the exact timing behavior of a 74HC74 dual D-flip-flop directly from the rectangular block without needing to open the datasheet.
