Designing a Band Pass Filter RLC Circuit: Topology, Values, and Testing

A series band pass filter RLC circuit passes a specific frequency band while attenuating signals above and below it, relying on the exact cancellation of inductive and capacitive reactance at resonance. If you need a center frequency of 15.9 kHz with a Q factor of 10, you need a 10 mH inductor, a 10 nF C0G capacitor, and a 100 Ω resistor. Unlike active op-amp filters, this passive topology requires no power rails, introduces zero active noise, and scales cleanly into the VHF range.

The Core Topology: Series RLC vs. Active Alternatives

When designing a band pass filter, you generally choose between an active topology (like a Sallen-Key op-amp circuit) or a passive RLC tank. The series RLC band pass topology routes the input signal through an inductor (L), a capacitor (C), and a resistor (R) to ground. The output voltage is measured across the resistor.

Node Labels & Signal Path:

• V_in: AC signal source enters the circuit.
• Node A: Junction between the inductor and capacitor.
• Node B: Junction between the capacitor and resistor.
• V_out: Measured across the resistor (Node B to Ground).

Why choose this passive topology over an active op-amp alternative? Active filters are excellent for low-frequency audio (sub-20 kHz) because they can provide gain and don't suffer from the insertion loss of passive components. However, active filters hit a hard wall at higher frequencies due to the op-amp's Gain-Bandwidth Product (GBP). A standard TL072 op-amp struggles to maintain accurate filter shapes above 100 kHz. A passive RLC circuit, conversely, is limited only by the self-resonant frequency (SRF) of the inductor and the parasitic capacitance of the PCB, allowing it to operate flawlessly into the tens of megahertz. Furthermore, passive RLC circuits handle high-voltage RF signals without the clipping and slew-rate distortion inherent to active silicon.

Design Walkthrough: Building a 15.9 kHz Telemetry Filter

Let's design a physical circuit with off-the-shelf components. Our target is a center frequency ($f_c$) of roughly 15.9 kHz (which is exactly 100 krad/s) with a Quality factor ($Q$) of 10, yielding a bandwidth of 1.59 kHz.

1. Select the Capacitor (C)
We start with the capacitor because standard values are more rigid than inductors. We select 10 nF. Crucially, you must specify a C0G (NP0) dielectric. Do not use X7R or Y5V ceramics; their capacitance shifts drastically with applied voltage and temperature, which will detune your filter under real-world signal loads. A KEMET C315C103K5G5TA (10 nF, 50V, C0G) is an ideal bench part.

2. Calculate the Inductor (L)
The resonance formula is $f_c = \frac{1}{2\pi\sqrt{LC}}$. Rearranging for L:
$L = \frac{1}{(2\pi f_c)^2 C}$
Plugging in $f_c = 15,915$ Hz and $C = 10 \times 10^{-9}$ F, we get $L = 0.01$ H, or 10 mH.

3. Calculate the Resistor (R) for Target Q
In a series RLC circuit, the Q factor is defined as $Q = \frac{\omega_0 L}{R}$, where $\omega_0 = 2\pi f_c$.
$10 = \frac{100,000 \times 0.01}{R}$
$R = \frac{1000}{10} = $ 100 Ω.

Component Behavior & Failure Mode Matrix

Understanding how each component dictates the filter's shape is critical for debugging. According to foundational AC theory outlined by Electronics Tutorials on Series Resonance, the interplay between L and C sets the frequency, while R sets the damping.

What Breaks at the Extremes (Failure Modes)

When troubleshooting a dead board, you must contrast series vs. parallel failure behaviors. In our series topology:

• Open Inductor or Open Capacitor: The signal path is physically broken. Zero output at all frequencies. The circuit fails completely.
• Shorted Capacitor: The capacitive reactance drops to zero. The circuit degenerates into a simple RL high-pass filter. Low frequencies are blocked, but high frequencies pass straight to the resistor.
• Shorted Resistor: $R$ becomes 0 Ω. The Q factor approaches infinity (theoretically), but your output voltage $V_{out}$ drops to 0V because you are measuring across a short. In reality, the massive current spike will likely blow your function generator's output fuse or saturate the inductor core.
• Open Resistor: No current flows, but if you measure with a high-impedance oscilloscope probe (10 MΩ), the probe itself becomes the resistor. You will see an incredibly narrow, high-Q spike at resonance, heavily distorted by the probe's 15 pF parasitic capacitance.

Decision Tree: Selecting Your Inductor and Topology

Inductor selection is where most RLC designs fail. Use this decision matrix to lock in your physical components based on your operating environment. For a deeper look at how component parasitics affect high-Q circuits, refer to the All About Circuits guide on Quality Factor.

The Default Recommendation: If you are breadboarding a sub-100 kHz filter for a microcontroller ADC front-end or audio crossover, terminate your search and buy the Bourns 78F103K-TR-RC. Its 10 mH value is standard, its physical footprint fits standard 0.1" breadboard spacing, and its ~18 Ω DCR is predictable enough to compensate for with your series resistor.

Breadboard Testing Protocol

Do not trust simulation software blindly; parasitic breadboard capacitance (typically 2-5 pF per contact strip) will shift your high-frequency resonance. Follow this exact bench procedure to characterize your physical build.

1. Prep the Board: Insert the Bourns 10 mH inductor, 10 nF C0G capacitor, and your calculated compensation resistor (e.g., 82 Ω) in series. Ensure the ground rail is continuous and low-impedance.
2. Setup Instruments: Connect a function generator to $V_{in}$. Set it to a 1.0 Vpp sine wave with 0V DC offset. Connect Oscilloscope CH1 to $V_{in}$ and CH2 to $V_{out}$ (across the resistor). Use 10x probes on both channels to minimize capacitive loading.
3. Find the Peak: Set the function generator to 15.9 kHz. Adjust the frequency slightly up and down until CH2 shows the maximum peak-to-peak voltage. Note this exact frequency as your true $f_c$.
4. Measure Insertion Loss: At $f_c$, the impedance of L and C cancel out, leaving only $R_{total}$ (external R + inductor DCR). Calculate expected $V_{out}$ using the voltage divider rule: $V_{out} = V_{in} \times (\frac{R_{external}}{R_{external} + DCR + R_{source}})$. If your scope reading is significantly lower, your inductor core is likely saturating or you have a breadboard contact resistance issue.
5. Plot the -3dB Points: Calculate 70.7% of your peak $V_{out}$ voltage. Sweep the frequency downward until CH2 hits this voltage; record as $f_1$. Sweep upward until it hits this voltage again; record as $f_2$. Your measured Bandwidth is $f_2 - f_1$. Divide $f_c$ by this bandwidth to verify your real-world Q factor.

By anchoring your design in C0G dielectrics, compensating for inductor DCR, and verifying the -3dB points with 10x scope probes, your band pass filter RLC circuit will perform exactly as the math dictates, without the hidden parasitic surprises that plague naive prototypes.