An avalanche photodiode (APD) is not just a standard PN junction with extra voltage; its internal construction fundamentally dictates how you must bias, decouple, and amplify it on the bench. Unlike a standard PIN photodiode that generates one electron-hole pair per photon, an APD exploits impact ionization to create internal current gain (multiplication). To achieve this without destroying the silicon, the avalanche photodiode construction relies on a specialized 'reach-through' epitaxial structure and physical guard rings. If you ignore the guard ring terminal or fail to temperature-compensate the high-voltage bias, your APD will either drown in dark current noise or suffer catastrophic thermal runaway.
For general-purpose visible to near-infrared (NIR) lab work, the Hamamatsu S8664-1010 (1.0 x 1.0 mm active area, ~150V breakdown) is the safest default pick. Below is the complete breakdown of how these devices are built, how to wire them, and how to verify them on the bench.
Avalanche Photodiode Construction and Symbol Pinout
The standard silicon APD uses a reach-through p+−π−p−n+ structure. Understanding this layer stack is critical because it defines the device's capacitance and breakdown behavior.
- p+ layer: The heavily doped window layer where light enters.
- π (pi) layer: A lightly doped, wide depletion region. This is the 'drift' region where photons are absorbed and primary electron-hole pairs are generated. Because it is wide, it lowers the junction capacitance (typically 1pF to 5pF), which is vital for high-speed transimpedance amplifier (TIA) circuits.
- p layer: The high-field multiplication region. Electrons drifting from the π layer accelerate here, gaining enough kinetic energy to knock secondary electrons loose (impact ionization).
- n+ substrate: The heavily doped base contact.
The Guard Ring and Pinout
High electric fields naturally concentrate at the curved edges of the PN junction, causing premature edge breakdown before the central active area reaches the avalanche threshold. To prevent this, APD construction incorporates a guard ring—a diffused ring surrounding the main junction that smoothly grades the electric field at the edges.
Standard TO-18 / TO-46 Pinout (3-Pin Package):
- Pin 1 (Anode): The signal output. Connects to the virtual ground of your TIA.
- Pin 2 (Guard Ring): Must be biased at a voltage slightly lower than the cathode, or tied to a specific guard bias. In many basic circuits, it is tied to the cathode or left floating per the datasheet, but tying it to the cathode via a high-value resistor prevents edge leakage from entering the signal path.
- Case (Cathode): The high-voltage bias input. In the Hamamatsu S8664 series, the metal can is the cathode.
Circuit Symbol: The schematic symbol is a standard photodiode (diode with inward-pointing arrows) enclosed in a circle or marked with a multiplication sign (×) near the cathode, denoting the internal gain region.
Operation Regions and Bias Requirements
APDs operate in two distinct regions depending on the applied reverse bias relative to the breakdown voltage (Vbr). Standard analog APDs operate in linear mode, while Single-Photon Avalanche Diodes (SPADs) operate in Geiger mode.
| Region | Bias Voltage (Vr) | Internal Gain (M) | Dark Current | Primary Application |
|---|---|---|---|---|
| Linear Mode | 0.8 × Vbr to 0.99 × Vbr (Typ: 30V - 200V) | 10 to 500 | 0.1 nA to 5 nA (pre-multiplication) | Analog optical receivers, LIDAR, spectroscopy |
| Geiger Mode (SPAD) | > Vbr (Typ: 5V to 50V overvoltage) | 10^5 to 10^7 | Quenched via active/passive circuits | Single-photon counting, PET scanners, dToF |
| PIN Mode (Sub-threshold) | 10V to 30V (Well below Vbr) | 1 (No multiplication) | < 1 pA | High-light conditions where gain causes saturation |
The breakdown voltage of a silicon APD is not static. It shifts by approximately +0.10V to +0.20V per °C. If your lab temperature rises from 20°C to 30°C, a fixed 150V bias might drop your gain from M=100 to M=40. For stable analog performance, your high-voltage bias supply must include a thermistor-based temperature compensation network, or you must use a dedicated APD bias controller IC like the MAX1932.
Complete Transimpedance Application Circuit
Because APDs output current, not voltage, you must use a Transimpedance Amplifier (TIA). The high reverse bias voltage (often 100V+) means you cannot simply place the APD in the feedback loop of a standard op-amp. The standard topology is low-side sensing, where the APD anode sits at virtual ground.
Component List and Values (For Hamamatsu S8664-1010)
- U1 (Op-Amp): Texas Instruments OPA656 (FET-input, 500MHz GBW, low input bias current of ~2pA). FET inputs are mandatory to avoid loading the high-impedance APD node.
- Rf (Feedback Resistor): 1 MΩ (0.1% tolerance, 0805 SMD to minimize parasitic capacitance).
- Cf (Feedback Capacitor): 1.2 pF (NP0/C0G ceramic). This compensates for the APD junction capacitance (~2pF) and prevents TIA oscillation.
- Rbias (Bias Isolation Resistor): 100 kΩ. Limits current during transient spikes and isolates the HV supply noise from the APD.
- Decoupling Network: 10 µF Tantalum in parallel with 100 nF and 10 nF MLCC ceramics, placed within 5mm of the APD cathode.
Wiring Sequence
- Connect the HV Bias Supply (+150V nominal) to one end of the 100 kΩ Rbias resistor.
- Connect the other end of Rbias to the APD Cathode (Case). Tie the APD Guard Ring (Pin 2) to the Cathode via a 10 kΩ resistor to bleed off edge leakage.
- Place the decoupling capacitors directly between the APD Cathode node and analog ground.
- Connect the APD Anode (Pin 1) directly to the Inverting Input (-) of the OPA656.
- Connect the OPA656 Non-Inverting Input (+) to a clean analog ground reference.
- Place Rf (1 MΩ) and Cf (1.2 pF) in parallel between the OPA656 Inverting Input and the Output pin.
For a deeper dive into stabilizing the feedback loop against parasitic PCB capacitance, refer to the Texas Instruments photodiode front-end design guide.
Failure Modes and Multimeter Testing
APDs are fragile. The most common failure modes are ESD destruction of the thin multiplication layer and thermal runaway caused by inadequate heat sinking or lack of temperature compensation, which drives the dark current until the junction melts.
How to Test an APD with a Digital Multimeter (DMM)
You can verify the basic health of the PN junction using the Diode Test mode on a standard bench DMM (like a Fluke 87V). Always test the APD out-of-circuit.
- Forward Bias Test: Place the red probe on the Anode (Pin 1) and the black probe on the Cathode (Case). A healthy silicon APD will read between 0.400 V and 0.650 V. (Note: This is lower than a standard rectifier diode due to the specific doping profiles).
- Reverse Bias Test: Swap the probes (Red to Cathode, Black to Anode). The DMM must read 'OL' (Over-Limit) or open circuit.
A standard DMM cannot test the avalanche breakdown voltage (Vbr). The diode test mode only outputs ~2V to 3V. If your APD reads 'OL' in reverse, it only proves the junction isn't shorted at 3V. To verify the actual Vbr and multiplication curve, you must use a semiconductor curve tracer or a precision source-measure unit (SMU) like a Keithley 2400, sweeping the voltage in 0.5V increments while monitoring dark current in a dark box.
Diagnostic Cheat Sheet:
- 0.000 V in Forward & Reverse: Dead short. Junction destroyed by ESD or overvoltage. Replace part.
- 'OL' in Forward & Reverse: Open circuit. Internal wire bond has snapped or lifted. Replace part.
- Reads a voltage (e.g., 1.2V) in Reverse: The junction is heavily leaking, or you are measuring ghost voltage from a charged decoupling capacitor on the PCB. Discharge the board and re-test.
Selection Decision Tree and Safe Default Picks
Selecting the right APD requires matching the target wavelength to the semiconductor bandgap, and matching the light intensity to the operation mode. Use this decision matrix to lock in your part number.
| Target Wavelength | Light Level | Required Material | Operation Mode | Concrete Default Part Pick |
|---|---|---|---|---|
| 400 nm to 1000 nm | Nanowatts to Microwatts (Analog) | Silicon (Si) | Linear | Hamamatsu S8664-1010 (TO-18, 1x1mm, Vbr ~150V) |
| 900 nm to 1700 nm | Nanowatts (Telecom/LIDAR) | InGaAs / InP | Linear | Hamamatsu G8931-20 (InGaAs, 20µm active area) |
| 400 nm to 1000 nm | Single Photons (Quantum/dToF) | Silicon (Si) | Geiger (SPAD) | onsemi MicroFC-10035-SMT (SiPM, 10x10 array) |
| 200 nm to 400 nm | UV Fluorescence / Flame Sensing | Silicon Carbide (SiC) | Linear | sglux SiC APD (Solar-blind UV detection) |
The Safe Default for the Bench: Hamamatsu S8664-1010
If you are building a generic optical receiver, a DIY LIDAR prototype, or a spectrometer and need a reliable, well-documented silicon APD, buy the Hamamatsu S8664-1010.
Why this specific part?
- Availability & Documentation: Hamamatsu provides exhaustive characterization data, including exact dark current vs. temperature graphs and gain vs. bias curves, which are mandatory for designing the TIA feedback network.
- Manageable Vbr: At ~150V nominal breakdown, you can safely generate the bias voltage using a low-noise boost converter (like the LT3482) without needing lethal high-voltage safety interlocks on your PCB.
- Low Capacitance: The 1.0 mm x 1.0 mm active area yields a junction capacitance of roughly 2.5 pF at 90% Vbr, allowing you to achieve TIA bandwidths well into the tens of megahertz without resorting to exotic RF op-amps.
When designing your PCB, keep the APD anode trace to the op-amp under 3mm in length, use a ground pour directly beneath the TIA to shield against EMI, and always include a physical light shield over the TO-18 can to prevent ambient room light from saturating your high-gain front end.
