The correct symbol of gates on a schematic depends entirely on the drafting standard used by the engineer. In the US and legacy military designs, the ANSI/IEEE Std 91a standard uses distinct geometric shapes (D-shapes for AND, curved shapes for OR). In Europe and modern international CAD environments, the IEC 60617-12 standard uses uniform rectangular boxes with internal alphanumeric codes. Below is the complete translation matrix between the two standards, including Boolean expressions and standard silicon part numbers.
Complete Logic Gate Symbol Reference Chart
| Gate Type | Boolean Expression | ANSI/IEEE Shape (US/Mil-Spec) | IEC 60617 Shape (EU/Intl) | Standard TTL/CMOS ICs |
|---|---|---|---|---|
| AND | Y = A · B | D-shape (flat back, curved front) | Rectangle with & inside | 74HC08, 74LS08, CD4081 |
| OR | Y = A + B | Curved back, pointed front | Rectangle with ≥1 inside | 74HC32, 74LS32, CD4071 |
| NOT (Inverter) | Y = A' | Triangle with output bubble | Rectangle with 1 inside | 74HC04, 74LS04, CD4069 |
| NAND | Y = (A · B)' | D-shape with output bubble | Rectangle with & and output bubble | 74HC00, 74LS00, CD4011 |
| NOR | Y = (A + B)' | Curved shape with output bubble | Rectangle with ≥1 and output bubble | 74HC02, 74LS02, CD4001 |
| XOR | Y = A ⊕ B | D-shape with extra curved back line | Rectangle with =1 inside | 74HC86, 74LS86, CD4030 |
| XNOR | Y = (A ⊕ B)' | XOR shape with output bubble | Rectangle with =1 and output bubble | 74HC266, CD4077 |
ANSI/IEEE vs. IEC: Which Standard Applies to You?
Choosing the right symbol of gates for your own schematics—or correctly interpreting someone else's—requires knowing which standard governs the drawing. According to the All About Circuits Digital Handbook, mixing these standards on a single schematic is a primary cause of miswiring in complex digital boards.
ANSI/IEEE Std 91a (The Shape-Based Standard)
Dominant in the United States, legacy military schematics, and hobbyist platforms like Fritzing or EasyEDA. The shapes are mnemonic: the flat back of the AND gate represents a "wall" that requires all inputs to push through, while the curved back of the OR gate represents a "funnel" where any input can slide to the output. If you are reading schematics from US-based defense contractors, automotive ECUs designed in the US, or older Texas Instruments logic datasheets, you will see these shapes.
IEC 60617-12 (The Rectangular Standard)
Mandatory in the EU and heavily used in international industrial automation (PLC programming, EPLAN schematics). The IEC standard rejects mnemonic shapes in favor of uniform rectangles. The logic function is defined strictly by the internal text: & for AND, ≥1 for OR (meaning one or more inputs must be high), and =1 for XOR (meaning exactly one input must be high). Inversion is always denoted by a small circle (bubble) on the pin, never by changing the box shape. The IEC 60617-12 standard documentation explicitly defines this to ensure language and shape-interpretation barriers are eliminated in global manufacturing.
The "Rows People Get Wrong" & Faded IC Identification
Schematic Traps: De Morgan's and Bubble Pushing
The most common mistake when reading the symbol of gates on a professional schematic is misidentifying De Morgan's equivalent gates. Engineers frequently use "bubble pushing" to make signal polarity readable. For example, an OR gate drawn with inversion bubbles on its inputs and its output is logically identical to a NAND gate. If you see an OR shape with three bubbles, do not go to the store for a specialized part; it is just a standard 74HC00 NAND gate drawn in "negative logic" to show that it triggers on active-low signals. Always trace the bubbles: if an output bubble connects directly to an input bubble, they cancel out.
Bench Troubleshooting: Identifying Faded or Sanded Logic ICs
When repairing industrial control boards or reverse-engineering proprietary hardware, you will often encounter logic ICs with faded silk-screen labels or intentionally sanded "black top" markings. Here is the safe, systematic protocol to identify the gate type without relying on visual markings.
- Locate Pin 1: Look for a microscopic chamfered edge, a laser-etched dot, or a slight indentation on the IC package. If sanded, use a multimeter in continuity mode to find the ground plane pins (usually Pin 7 on 14-pin DIPs) to orient the chip.
- Power with Current Limiting: Set your bench power supply to 5.0V with a strict 50mA current limit. Connect VCC (Pin 14) and GND (Pin 7). If the supply hits the 50mA limit and voltage drops, your pinout assumption is wrong or the IC is dead.
- Map the Truth Table: Use a logic probe or a multimeter set to DC voltage. Tie unused inputs to GND (never leave CMOS inputs floating, or they will oscillate and overheat). Inject a 5V pulse into the suspected input pins and record the output. Compare your physical truth table against the reference chart above to identify the exact gate.
Frequently Asked Questions
What is the symbol of gates in PLC ladder logic?
In Programmable Logic Controller (PLC) environments governed by IEC 61131-3, the traditional logic gate symbols are rarely used in Ladder Diagram (LD) view. Instead, AND gates are represented by series contacts (two vertical lines in a row), and OR gates are represented by parallel branches (contacts stacked vertically). However, if you are programming in Function Block Diagram (FBD) mode within the same PLC software, the software will revert to the IEC 60617 rectangular symbols (& and ≥1) to represent the logic gates.
Why do schematics use weird inverted symbol of gates shapes?
This is a deliberate design choice called "active-low logic notation." In many digital systems, critical signals like RESET, CHIP_SELECT, or INTERRUPT are active-low (they trigger when the voltage drops to 0V). To prevent the engineer reading the schematic from having to mentally invert the signal, the drafter will change the symbol of the gate. A standard AND gate might be drawn as an OR gate with bubbles on all pins. This visually communicates: "This gate outputs a LOW signal when ANY of its inputs go LOW." It is electrically the exact same silicon, just drawn to match the logical intent.
How do I know if a logic gate IC is TTL or CMOS from the schematic?
The symbol of gates on the schematic does not change between TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide-Semiconductor), but the part number prefix does. If the schematic calls out a 74LS or 74F prefix (e.g., 74LS08), it is TTL, requires a strict 5V ±5% supply, and has asymmetric drive strength (sinks current well, sources poorly). If it calls out 74HC, 74HCT, or CD40, it is CMOS. CMOS gates have symmetrical push-pull outputs, draw near-zero quiescent current, and can operate across a wider voltage range (2V to 6V for HC, up to 15V for CD40 series). Never substitute a 74LS chip for a 74HC chip in a 3.3V microcontroller circuit; the TTL chip will fail to register the 3.3V logic high.
