Digital logic schematics use two dominant standards to represent basic Boolean operations. If you are reading a US-based datasheet or textbook, you will see distinctive shapes (ANSI/IEEE). If you are reading European or modern international PLC diagrams, you will see rectangular blocks (IEC). Here is the complete mapping.
Complete AND and OR Gate Symbol Reference
| Gate Type | ANSI/IEEE Symbol (US) | IEC 60617 Symbol (Intl) | Boolean Expression | Truth Table (A, B → Y) |
|---|---|---|---|---|
| 2-Input AND | D-shaped (flat back, curved front) | Rectangle with '&' inside | Y = A · B | 0,0→0 | 0,1→0 | 1,0→0 | 1,1→1 |
| 2-Input OR | Curved back, pointed front | Rectangle with '≥1' inside | Y = A + B | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 |
| 3-Input AND | D-shape with 3 input lines | Rectangle with '&' and 3 inputs | Y = A · B · C | Outputs 1 only when A=1, B=1, C=1 |
| 3-Input OR | Curved back, pointed front, 3 inputs | Rectangle with '≥1' and 3 inputs | Y = A + B + C | Outputs 1 if any input (A, B, or C) is 1 |
| Buffer (1-Input) | Triangle pointing right | Rectangle with '1' inside | Y = A | 0→0 | 1→1 |
Regional Standards and IC Pinout Mapping
The shape of the symbol on your schematic depends entirely on the drafting standard used by the engineer. In the United States, ANSI/IEEE Std 91-1984 dictates the use of 'distinctive shapes' (the D-shape for AND, the curved shield for OR). These shapes are deeply ingrained in American university curricula and legacy military/aerospace schematics.
Internationally, and increasingly in modern CAD software (like Altium or KiCad default libraries), the IEC 60617-12 standard is preferred. IEC uses uniform rectangular blocks. The logic function is indicated by a qualifier inside the box: an ampersand (&) for AND, and a greater-than-or-equal-to-one symbol (≥1) for OR. The IEC standard scales better in complex PLC ladder logic and dense FPGA block diagrams because rectangles pack neatly into grid layouts without overlapping curved lines.
When wiring physical AND/OR gate ICs on a breadboard, never rely solely on the logic symbol. Always verify the VCC and GND pins. For standard 14-pin DIP logic ICs, Pin 14 is VCC (Positive) and Pin 7 is GND. Reversing these will instantly destroy the silicon junction inside the chip.
Here are the exact part numbers and pinouts for the most common through-hole AND and OR gate ICs you will encounter at the bench:
| Function | Standard Part Number | CMOS Equivalent | Operating Voltage | Package / Pinout |
|---|---|---|---|---|
| Quad 2-Input AND | 74LS08 / 74HC08 | CD4081B | HC: 2V-6V | LS: 4.75V-5.25V | 14-pin DIP (4 independent gates) |
| Quad 2-Input OR | 74LS32 / 74HC32 | CD4071B | HC: 2V-6V | LS: 4.75V-5.25V | 14-pin DIP (4 independent gates) |
| Triple 3-Input AND | 74LS11 / 74HC11 | CD4023B | HC: 2V-6V | LS: 4.75V-5.25V | 14-pin DIP (3 independent gates) |
For detailed electrical characteristics, propagation delays, and absolute maximum ratings, always consult the manufacturer's specific datasheet, such as the Texas Instruments SN74HC08 Datasheet. Note that 'HC' (High-speed CMOS) parts have high-impedance inputs that will float and cause erratic switching if left unconnected; always tie unused inputs to VCC or GND via a 10kΩ resistor.
Rows and Symbols People Get Wrong
Even experienced technicians misread logic schematics when dealing with inverted logic or poorly preserved documents. Here are the most common pitfalls.
The 'Bubble' Confusion (NAND/NOR vs AND/OR)
A small circle (bubble) on the output or input of a gate indicates logical inversion (NOT). An AND gate with a bubble on the output is a NAND gate. An OR gate with a bubble on the output is a NOR gate. In IEC notation, this is represented by a small triangle or a circle on the output line, or by adding a bar over the Boolean expression. Never assume a gate is a standard AND/OR if the output line has a break or a circle in it.
De Morgan's Equivalents in Schematic Drafting
Engineers frequently use De Morgan's Theorem to draw gates in 'negative logic' to make schematics easier to read. For example, a NAND gate (AND shape with output bubble) is logically identical to an OR gate with bubbles on its inputs (Negative-OR). If you see an OR shape with bubbles on the inputs and no bubble on the output, it is physically a NAND gate. Draftsmen do this so that the bubbles cancel out with active-low enable pins on downstream ICs. For a deeper dive into these transformations, review the All About Circuits Digital Logic Gates tutorial.
Safe Interpretation of Faded or Torn Schematics
When working on legacy industrial equipment, you will often encounter schematics where the ink has faded, making the distinctive ANSI curves look like smudged blobs. How to safely interpret them:
- Look for the inversion bubble: Even if the body is faded, the output bubble (if present) is usually distinct. If there is a bubble, it is a NAND/NOR. If not, it is AND/OR.
- Check the IEC qualifier: If it is a rectangular block, look closely at the center. A faint '&' means AND; a faint '≥1' means OR.
- Trace the logical intent: If the gate is combining multiple 'enable' or 'chip select' lines, it is almost certainly an AND gate (all conditions must be true). If it is combining multiple 'fault' or 'interrupt' lines, it is almost certainly an OR gate (any fault triggers the alarm).
Frequently Asked Questions
What is the difference between ANSI and IEC logic gate symbols?
ANSI/IEEE Std 91 uses 'distinctive shapes' where the physical outline of the symbol indicates its function (a D-shape for AND, a curved shield for OR). IEC 60617-12 uses uniform rectangular blocks for all gates, relying on text qualifiers inside the box (like '&' for AND or '≥1' for OR) to define the logic. ANSI is standard in US academia and legacy prints; IEC is standard in international PLC programming and modern European CAD designs.
How do I safely interpret a logic gate symbol if the schematic is faded or torn?
First, look for an inversion bubble (a small circle) on the output or inputs, which changes an AND/OR into a NAND/NOR. If the shape is entirely illegible, trace the circuit logic: gates combining multiple permissive/enable signals are typically AND gates, while gates combining multiple alarm/interrupt signals are typically OR gates. If using an IEC block, use a magnifying glass to check for the '&' or '≥1' qualifier inside the rectangle.
Why do some AND gate symbols have more than two input lines?
A 3-input or 4-input AND gate requires all inputs to be HIGH (1) for the output to go HIGH. In physical ICs, this is achieved by adding more transistors in series within the silicon die. On a schematic, this is drawn simply by adding more input lines to the left side of the standard AND shape or IEC rectangle. The Boolean expression expands accordingly (e.g., Y = A · B · C).
What are the standard 74-series IC part numbers for AND and OR gates?
The most common through-hole DIP ICs are the 74HC08 (Quad 2-Input AND) and the 74HC32 (Quad 2-Input OR). The 'HC' denotes High-speed CMOS, which operates from 2V to 6V. Older 'LS' (Low-power Schottky) variants like the 74LS08 and 74LS32 require a strict 5V TTL supply. For 3-input gates, the 74HC11 provides three independent 3-input AND gates in a single 14-pin package.
