When reading a digital schematic, the logic gate symbols you encounter depend entirely on the standard the designer chose. In the US and in most hobbyist literature, you will see ANSI/IEEE 91-1984 distinctive shapes (the classic D-shapes and curves). In European industrial designs, modern CAD tools, and PLC ladder logic, you will see IEC 60617-12 rectangular blocks. Understanding both is mandatory for bench troubleshooting and cross-border engineering work.

The Complete Logic Gates Symbol Reference Table

The table below maps the core logic functions to their ANSI shapes, IEC rectangular codes, Boolean expressions, and the most common through-hole IC part numbers you will find in a parts bin.

Gate Name Boolean Function ANSI/IEEE Symbol Shape IEC 60617 Internal Code Standard IC (DIP-14)
AND Y = A · B D-shape (flat back, curved front) Rectangle with & 74HC08 / CD4081
OR Y = A + B Curved back, pointed front Rectangle with ≥1 74HC32 / CD4071
NOT (Inverter) Y = A' Triangle with output bubble Rectangle with 1 and output bubble 74HC04 / CD4069
NAND Y = (A · B)' D-shape with output bubble Rectangle with & and output bubble 74HC00 / CD4011
NOR Y = (A + B)' Curved back with output bubble Rectangle with ≥1 and output bubble 74HC02 / CD4001
XOR Y = A ⊕ B Double-curved OR shape Rectangle with =1 74HC86 / CD4030
XNOR Y = (A ⊕ B)' Double-curved OR with bubble Rectangle with =1 and output bubble 74HC266 / CD4077
Buffer Y = A Triangle (no bubble) Rectangle with 1 (no bubble) 74HC125 / CD4050

Regional Standards: ANSI vs. IEC vs. Legacy DIN

Unlike residential wiring color codes, logic symbols do not carry life-safety risks if misinterpreted, but they will absolutely cause you to miswire a breadboard or misprogram an FPGA if you confuse the standards.

  • ANSI/IEEE 91-1984 (Distinctive Shapes): The default in North American universities, US military schematics, and hobbyist platforms like Arduino/Fritzing diagrams. The shapes are designed to be instantly recognizable by silhouette, making them ideal for hand-drawn schematics and quick whiteboard debugging.
  • IEC 60617-12 (Rectangular): The standard in Europe, modern EDA tools (like Altium and KiCad's default European libraries), and industrial automation. Instead of memorizing shapes, you read the function code inside the box. This scales much better for complex, custom ASIC blocks where a distinctive shape doesn't exist.
  • Legacy DIN 40700 (German): Mostly obsolete since the 1990s, but you will still encounter these on vintage Siemens, Telefunken, and Philips test equipment from the 1970s and 80s. DIN used semi-circles and rectangles with different internal notations. If you are restoring vintage bench gear, keep a DIN cheat sheet handy.
Bench Warning: When importing third-party SPICE models or CAD footprints, always verify which symbol standard the library uses. Mixing IEC rectangular symbols with ANSI netlist naming conventions in complex hierarchical sheets frequently leads to unconnected pins during PCB layout.

Rows People Get Wrong (and How to Fix Them)

Even experienced engineers misread specific gates when scanning dense schematics. Here are the most common points of failure on the bench:

  1. XOR vs. OR in IEC Schematics: The difference between an OR gate (≥1) and an XOR gate (=1) is a single character. In a densely routed schematic where the text is scaled down, the 'greater than' sign in ≥1 easily disappears, making an OR gate look like an XOR. Fix: Always zoom in on the qualifier text, or check the BOM for the part number (7432 vs 7486).
  2. Inversion Bubbles on Inputs vs. Outputs: A NAND gate drawn with an output bubble is logically identical to an OR gate drawn with input bubbles (De Morgan's Theorem). Designers sometimes use 'bubble pushing' to make a schematic read more logically, but this obscures the actual physical IC pinout. Fix: Trace the netlist back to the physical IC pinout; the physical silicon doesn't care about De Morgan's visual tricks.
  3. Schmitt Trigger Hysteresis: A standard buffer is just a triangle. A Schmitt trigger buffer (like the 74HC14) includes a small hysteresis loop symbol (a lazy-S or box-within-a-box) inside the triangle. Missing this symbol means you might substitute a standard buffer, resulting in severe oscillation on noisy, slow-rising input signals.
  4. 3-Input and 4-Input Gates: The table above shows 2-input gates. A 3-input AND gate is simply an ANSI D-shape with three input lines, or an IEC rectangle with an & and three input lines (e.g., the 74HC10 triple 3-input NAND). Beginners often assume all gates only have two inputs.

Safe Interpretation When Markings Are Faded or Missing

When you are salvaging components or repairing a board where the silkscreen is burned off or the IC laser marking is worn away, you can deduce the logic gate by mapping its physical behavior.

For standard 14-pin DIP logic ICs (both 74xx TTL/CMOS and 40xx CMOS series), the power pins are almost universally Pin 14 (VCC) and Pin 7 (GND).

Voltage Safety Note: Standard 74LS (TTL) requires a strict 5V supply. 74HC (CMOS) can handle 2V to 6V. CD4000 series CMOS can handle 3V to 15V. Never apply 12V to a 74-series chip, or it will fail catastrophically and become hot enough to burn your fingers.

The Deduction Test Jig:
1. Apply the correct VCC to Pin 14 and GND to Pin 7.
2. Identify Pin 1 (usually marked by a dot or notch). For a standard quad 2-input package, the pins map as: Gate A (1, 2 in, 3 out), Gate B (4, 5 in, 6 out), Gate C (9, 10 in, 8 out), Gate D (12, 13 in, 11 out).
3. Use a 1kΩ resistor and an LED to pull inputs High or Low, and probe the output.
4. If both inputs High yields a Low output, you are holding a NAND (7400). If both High yields High, it is an AND (7408). If one High yields High, it is an OR (7432). If outputs toggle only when inputs differ, it is an XOR (7486).

Frequently Asked Questions

What is the difference between ANSI and IEC logic gate symbols?

ANSI/IEEE symbols use distinctive physical shapes (like the D-shape for AND) to represent functions, making them easy to recognize at a glance. IEC 60617 symbols use uniform rectangular blocks with internal alphanumeric codes (like & for AND or ≥1 for OR). ANSI is dominant in US academia and hobbyist circles, while IEC is the standard in European industrial design and modern EDA software.

How do I read an IEC rectangular logic symbol with no text inside?

An IEC rectangle with absolutely no internal text is technically non-compliant with IEC 60617-12, but in practice, it is often used as a generic non-inverting buffer or a placeholder for a custom ASIC macrocell. Check the input and output pin numbers against the datasheet for the specific IC. If it has a bubble on the output, it is an inverter, regardless of the missing internal text.

Why do some logic gate symbols have a circle on the output?

The small circle (often called a 'bubble') represents logical inversion (a NOT operation). An AND gate with a bubble on the output is a NAND gate. An OR gate with a bubble is a NOR gate. In IEC symbols, this is sometimes represented by a small triangle or a bar over the output pin number instead of a literal circle, depending on the CAD library used.

Are there logic gates with more than two inputs in standard symbols?

Yes. While 2-input gates are the most common, 3-input, 4-input, and even 8-input gates exist. In ANSI symbols, you simply draw more input lines entering the shape (e.g., a D-shape with three lines is a 3-input AND). In IEC symbols, the rectangle remains the same, but the internal code (like &) will have three or more input lines mapped to it. The 74HC10 (triple 3-input NAND) and 74HC21 (dual 4-input AND) are common bench examples.

For deeper reading on standard logic families and their electrical characteristics, refer to the Texas Instruments Standard Logic Portfolio and the foundational chapters on Logic Gates at All About Circuits.