The direct answer: For a 400V DC bus storing up to 100 Joules, the most reliable capacitor discharge circuit is an optocoupler-isolated N-channel MOSFET topology. Use an IRF840 MOSFET switched by a loss-of-AC signal, dumping energy through a 1.2kΩ pulse-rated wirewound resistor. This topology dissipates zero standby power during normal operation and guarantees a sub-50V discharge in under 3 seconds when mains power fails, satisfying IEC 62368-1 safety requirements without the contact-welding risks of mechanical relays.
The Decision Path: Passive vs. Active Discharge Topologies
When designing a discharge path for high-voltage DC link capacitors (like those in variable frequency drives, SMPS, or solar inverters), you must balance standby power loss, component cost, and fail-safe reliability. Here is the decision matrix to arrive at the optimal topology.
| Topology | Standby Power Loss | Discharge Speed | Failure Mode Risk | Verdict |
|---|---|---|---|---|
| Passive Bleeder Resistor | High (Continuous I²R loss) | Slow (Fixed RC time constant) | Resistor open-circuit = lethal shock hazard | Reject for >50V / >10J systems |
| Normally-Closed (NC) Relay | Zero (When mains is dead) | Fast (Low resistance path) | Contacts weld shut on high inrush; coil draws standby power | Reject for high-reliability solid-state designs |
| Opto-Isolated N-MOSFET | Zero (Opto draws <2mA from aux supply) | Fast & Tunable (Pulse resistor) | MOSFET short = thermal failure; Opto open = shock hazard | DEFAULT PICK: Opto-Isolated MOSFET |
Opto-Isolated MOSFET Topology: Node Labels and Operation
This circuit relies on an auxiliary AC-derived DC supply (V_AUX) to keep the discharge path disabled during normal operation. When AC mains drops, V_AUX collapses, triggering the discharge.
Node Definitions:
- V_DC+: The high-voltage main DC bus (e.g., 400V nominal).
- GND: The system common ground (tied to the negative terminal of the main DC bus capacitor).
- V_AUX: A low-voltage (12V-15V) supply derived from the AC mains via a small flyback or capacitive dropper.
- Gate_Node: The junction between the pull-up resistor, the Zener clamp, and the MOSFET gate.
- Drain_Node: The junction between the pulse discharge resistor and the MOSFET drain.
Operating States:
AC Mains ON: V_AUX powers the LED side of a PC817 optocoupler. The optocoupler's phototransistor turns on, pulling the Gate_Node to GND. The N-channel MOSFET (Q1) remains firmly OFF. The main capacitor charges and holds V_DC+.
AC Mains OFF: V_AUX collapses. The optocoupler LED turns off, and the phototransistor opens. A high-value pull-up resistor (R_pullup, e.g., 100kΩ) connected from V_DC+ to the Gate_Node pulls the gate high. A 12V Zener diode clamps the gate voltage to a safe level. Q1 turns on, connecting the Drain_Node to GND, and the main capacitor dumps its stored energy through the pulse resistor (R_drain).
Behavior Matrix: Component Shifts and Discharge Dynamics
Understanding how component tolerances and parasitic effects alter the discharge curve is critical for passing safety compliance audits. The RC discharging principles dictate the baseline, but real-world parasitics change the outcome.
| Element Changed | Direction of Change | Effect on Discharge Time | Effect on Peak Component Stress |
|---|---|---|---|
| R_drain (Pulse Resistor) | Increases (+20%) | Discharge time increases proportionally; may fail safety limits. | Peak I²R power decreases; resistor runs cooler. |
| C_main (DC Bus Cap) | Increases (End-of-life capacitance growth) | Discharge time increases; stored energy (Joules) increases significantly. | MOSFET must handle higher total thermal mass; risk of SOA violation. |
| V_AUX Decay Rate | Slower (Large aux filter cap) | Delays the turn-on of the MOSFET; creates a 'dead time' where bus remains lethal. | No direct stress change, but compromises safety timing. |
| Zener Clamp (12V) | Leaks prematurely | No effect on time. | Steals gate drive current from R_pullup; MOSFET may operate in linear region and overheat. |
Design Walkthrough: Sizing a 400V, 1000µF DC Bus
Let's size the components for a realistic motor drive DC bus. According to Vishay's RC design guidelines, pulse energy handling is the primary constraint for the discharge resistor.
1. Calculate Stored Energy:
E = 0.5 × C × V²
E = 0.5 × 0.001F × (400V)² = 80 Joules.
2. Determine Target Resistance:
Safety standards typically require the bus to drop below 60V (or 50V for stricter tiers) within 3 seconds of plug removal. Using the decay formula V(t) = V₀ × e^(-t/RC):
50 = 400 × e^(-3 / (R × 0.001))
0.125 = e^(-3000 / R)
ln(0.125) = -2.079 = -3000 / R
R ≈ 1442 Ω.
We will select a standard value of 1.2kΩ to provide a safety margin, yielding a time constant (τ) of 1.2 seconds. At 3 seconds (2.5τ), the voltage will drop to roughly 32V.
3. Select Real Components:
- R_drain: Ohmite 160 Series 1.2kΩ, 5W continuous, but rated for high pulse energy. A standard 5W carbon film resistor will explode from the 80J pulse. You must use a wirewound pulse resistor.
- Q1 (MOSFET): Vishay IRF840 (500V Vds, 8A Id). At 400V and 1.2kΩ, peak current is only 333mA. The IRF840 is massive overkill for current, but its large silicon die provides the thermal mass to absorb the 80J pulse without violating its Safe Operating Area (SOA).
- Optocoupler: Lite-On PC817 (Standard CTR, 5000Vrms isolation).
- Zener Diode: 1N4742A (12V, 1W) to protect the IRF840 gate oxide.
- R_pullup: 100kΩ, 1W metal oxide (must withstand 400V continuous).
Failure Modes: What Breaks at the Extremes
A robust design anticipates single-point failures. Here is what happens when components fail in this specific topology:
- Shorted MOSFET (Drain-to-Source): The 1.2kΩ resistor is permanently connected across the 400V bus. It will dissipate P = V²/R = 133 Watts continuously. A 5W pulse resistor will catch fire within seconds. Mitigation: Place a fast-acting 500V fuse in series with R_drain, or use a thermal cutoff embedded in the resistor winding.
- Open Optocoupler LED: The circuit behaves as if AC is always off. The capacitor discharges immediately upon charging. The power supply will fail to regulate because the DC bus is being constantly bled. Mitigation: This is a 'fail-safe' condition regarding shock hazard, but causes functional failure. Use an optocoupler with a high-reliability grade.
- Open Zener Diode: When AC fails, R_pullup pulls the gate all the way to 400V. The IRF840 gate oxide ruptures instantly (max Vgs is ±20V). The MOSFET fails short, leading to the thermal runaway described above. Mitigation: Never omit the Zener clamp, and consider adding a 1kΩ series gate resistor to limit the rupture current.
Step-by-Step Breadboard Validation (Low-Voltage Proxy)
Never breadboard a 400V discharge circuit directly. The stored energy is lethal, and arc flashes from slipped jumper wires can cause severe burns. Instead, build a scaled low-voltage proxy to validate the timing logic and MOSFET switching dynamics.
- Scale the Parameters: Use a 24V DC bench supply to simulate V_DC+. Use a 2200µF electrolytic capacitor. To maintain a similar RC time constant and observable discharge, use a 100Ω standard 1/4W resistor for R_drain.
- Simulate V_AUX: Use a second bench supply or a 5V USB line to power the PC817 LED side via a 220Ω current-limiting resistor. This represents your 'AC Mains ON' state.
- Wire the Gate Drive: Connect the 100kΩ R_pullup from the 24V bus to the Gate_Node. Connect the 12V Zener (or a 5.1V Zener for low-voltage testing) from Gate_Node to GND. Wire the optocoupler phototransistor from Gate_Node to GND.
- Instrument the Nodes: Connect Channel 1 of your oscilloscope to V_DC+ (the main capacitor). Connect Channel 2 to the Gate_Node. Set the scope to trigger on the falling edge of Channel 1.
- Execute the Test: Energize both supplies. Verify the capacitor charges to 24V and the Gate_Node reads ~0.2V (optocoupler saturation voltage). The MOSFET must remain OFF.
- Simulate Power Loss: Simultaneously cut power to the 24V main bus and the 5V optocoupler LED. (In a real circuit, the aux supply collapses slightly after the main bus due to hold-up caps, but simultaneous cutoff is the worst-case timing test).
- Analyze the Waveform: Verify that the Gate_Node spikes and clamps at the Zener voltage within microseconds. Verify the main capacitor voltage decays to <3V (proxy for 50V) within your calculated time constant. If the decay curve shows a 'step' or plateau, your MOSFET is entering the linear region due to insufficient gate drive; lower the value of R_pullup.
