Phase Shift and Impedance: Designing Filters in an AC Capacitive Circuit for ESP32 Sensors

When reading an alternating current (AC) signal—like the output of a current transformer (CT) or an AC microphone—with a unipolar microcontroller ADC, you face a fundamental problem: the signal swings below ground. To safely interface this with an ESP32 or Arduino, you must block the DC offset while shifting the AC waveform into the 0–3.3V window. The definitive solution is a series coupling capacitor paired with a resistive voltage divider bias network. In short, to properly condition a signal in an ac capacitive circuit for a 0-3.3V ADC, you need a high-pass RC filter biased to VCC/2 (1.65V). This guide provides the exact topology, real component values, and failure analysis to get it right on the first breadboard.

The Core Topology: AC Coupling with DC Bias

The standard AC coupling network consists of three primary components forming a high-pass filter and a DC bias reference. Understanding the node behavior is critical before you place a single component.

• Node A (AC Source): The raw AC signal input (e.g., the secondary leads of an SCT-013-000 current transformer). This node swings symmetrically around 0V.
• Node B (Coupling Junction): The intersection of the series coupling capacitor (C1) and the bias resistor network (R1 and R2). This node carries the AC signal superimposed on a DC offset.
• Node C (ADC Input): The final output to the microcontroller. This is typically identical to Node B, though sometimes a small series resistor (e.g., 100Ω) is added here for ADC charge-injection protection.

Why AC Coupling Wins Over Direct DC Clamping

You might wonder why we use a capacitive network instead of simply clamping the negative half-cycles with a Zener diode or a Schottky diode to ground. The answer lies in waveform integrity and phase preservation.

When you use a diode clamp, you brutally chop off the negative half of the AC waveform. For simple RMS calculations, software can sometimes compensate for half-wave rectification, but you lose all zero-crossing phase information. If your project requires calculating Real Power (Watts) or Power Factor, you must know the exact phase relationship between voltage and current. Diodes introduce non-linear junction capacitance and forward-voltage knee distortions that ruin phase accuracy.

By utilizing a capacitive coupling network, the capacitor acts as an open circuit to DC but a low-impedance path to AC. It preserves the full sinusoidal geometry. According to the OpenEnergyMonitor CT Interface Guide, maintaining the linear phase relationship is non-negotiable for accurate energy monitoring. Furthermore, the capacitor provides galvanic isolation for the DC bias network, preventing ground loops between the sensor and the microcontroller.

Design Walkthrough: Sizing Components for a 60Hz CT Sensor

Let us design a real interface for an SCT-013-000 (100A:50mA) current transformer monitoring a 60Hz mains circuit, feeding an ESP32 ADC. Our goal is to pass 60Hz with minimal phase shift while keeping power consumption low.

Step 1: Define the Bias Resistors (R1, R2)
We need a 1.65V bias (half of 3.3V). We use two identical resistors in series from 3.3V to GND. To minimize current draw from the ESP32's 3.3V regulator, we select high-value resistors. Let us choose 470kΩ for both R1 and R2. The DC bias is exactly 1.65V, and the static current draw is a negligible 3.5µA.

Step 2: Calculate the Thevenin Resistance
For the AC signal, the 3.3V rail and GND are effectively the same node (AC ground). Therefore, R1 and R2 are in parallel from the perspective of the AC signal.
R_th = (470kΩ × 470kΩ) / (470kΩ + 470kΩ) = 235kΩ

Step 3: Select the Cutoff Frequency (fc)
To avoid phase shift and amplitude attenuation at 60Hz, the high-pass cutoff frequency should be at least a decade below the target frequency. Let us target fc = 1Hz.

Step 4: Calculate Capacitance (C1)
Using the standard RC high-pass formula: C = 1 / (2π × R_th × fc)
C = 1 / (2 × 3.14159 × 235,000 × 1) = 0.678µF

Step 5: Pick the Concrete Component
The closest standard value is 1µF. Do not use a standard electrolytic capacitor here; their high Equivalent Series Resistance (ESR) and polarity sensitivity will distort the signal and risk reverse-bias damage. Instead, select a metallized polyester film capacitor.
Concrete Pick: WIMA MKS2 Series, 1µF, 50VDC (Mouser Part: MKS2D031001E00KSSD). This part has tight 10% tolerance, negligible dielectric absorption, and an ESR low enough to keep your phase angle pristine.

Failure Modes: What Breaks at the Extremes?

A robust design requires understanding exactly how the circuit fails when a component goes open or short. Here is the failure-mode contrast for this topology.

Notice that a shorted coupling capacitor is the only catastrophic failure mode. To mitigate this in high-reliability designs, place a 100Ω series resistor between Node B and Node C, and add back-to-back Schottky diodes (like the BAT54S) from Node C to VCC and GND to clamp any transient over-voltages safely.

Breadboard Testing and Verification Steps

Do not connect this circuit to live mains until you have verified the bias and coupling behavior on the bench. Follow this exact sequence using a function generator and an oscilloscope (or a logic analyzer with analog channels).

1. Verify the DC Bias (Power Only): Power the ESP32 or breadboard 3.3V rail. Leave Node A disconnected. Measure Node C with a multimeter. It must read between 1.60V and 1.70V. If it reads 0V or 3.3V, check R1 and R2 for breadboard contact issues.
2. Inject a Safe AC Signal: Set your function generator to output a 60Hz sine wave, 2.0V peak-to-peak, with a 0V DC offset. Connect the generator output to Node A, and connect the generator ground to the breadboard ground.
3. Observe the AC Shift: Probe Node A and Node C simultaneously on your oscilloscope. Node A should show a sine wave centered at 0V (swinging -1V to +1V). Node C should show the exact same sine wave, but centered at 1.65V (swinging 0.65V to 2.65V).
4. Measure Phase Shift: Trigger the scope on the rising zero-crossing of Node A. Measure the time delay to the rising 1.65V-crossing of Node C. At 60Hz with a 1Hz cutoff frequency, the phase shift should be less than 2 degrees (a time delay of < 90µs). If the delay is massive, your capacitor value is too small or your bias resistors are lower than calculated.
5. Test the Clipping Extremes: Increase the function generator amplitude to 5.0V peak-to-peak. Verify that the signal at Node C attempts to swing outside 0-3.3V, and confirm that your software correctly identifies the clipped peaks (or that your external Schottky clamps are engaging if installed).

Decision Tree: Picking Your Exact Coupling Capacitor

The behavior of the signal in an ac capacitive circuit is entirely dependent on the dielectric material of the capacitor you choose. Do not default to whatever is in your junk bin. Use this decision matrix to select the correct part for your specific frequency band.

For 95% of hobbyist and maker energy-monitoring projects operating at mains frequencies, the WIMA MKS2 1µF film capacitor paired with 470kΩ bias resistors is the definitive, default choice. It provides the exact impedance needed to keep your ESP32 ADC safely in the linear region while preserving the phase data required for accurate power factor calculations. Build it, bias it to 1.65V, and trust the math.