The standard 555 timer pinout follows the 8-pin DIP (Dual In-line Package) and SOIC configuration. Pin 1 is Ground (bottom-left, adjacent to the orientation notch) and Pin 8 is VCC (top-left). While the internal silicon has evolved from the original 1972 bipolar design to modern CMOS, the physical pin assignments remain strictly backward-compatible. Below is the direct reference data you need to wire this IC on the bench, followed by the specific failure modes and variant selections that separate a working circuit from a frustrating one.
The Complete 555 Timer Pinout Reference Table
This table assumes a standard top-down view of the IC with the orientation notch or dimple facing away from you (up). This pinout applies universally to the bipolar NE555, CMOS TLC555, and LMC555 variants.
| Pin | Name | Function | Practical Bench Notes |
|---|---|---|---|
| 1 | GND | Ground / 0V Reference | Must share a common ground plane with your timing capacitor and load. Keep the decoupling capacitor return path as short as possible to this pin. |
| 2 | TRIG | Trigger Input | Active low. Fires the output high when voltage drops below 1/3 VCC. Requires a pull-up resistor (e.g., 10kΩ to VCC) if driven by a mechanical switch. |
| 3 | OUT | Push-Pull Output | Sources and sinks current. Bipolar versions drop ~1.5V from VCC when high; CMOS versions are rail-to-rail. |
| 4 | RESET | Master Reset | Active low. Forces output low and discharges the timing cap. Never leave floating; tie directly to VCC if unused. |
| 5 | CTRL | Control Voltage | Accesses the internal 2/3 VCC voltage divider. Must be bypassed to GND with a 10nF ceramic capacitor to reject high-frequency noise. |
| 6 | THRES | Threshold Input | Monitors the timing capacitor. Resets the output low when voltage exceeds 2/3 VCC. High impedance; keep traces short. |
| 7 | DISCH | Discharge | Open-collector (bipolar) or open-drain (CMOS). Sinks current to discharge the timing capacitor. Does not source current. |
| 8 | VCC | Positive Supply | 4.5V to 16V for bipolar NE555; 2V to 15V for CMOS. Requires a 100nF decoupling capacitor placed within 2mm of Pins 8 and 1. |
Rows People Get Wrong (and How to Fix Them)
Even experienced makers routinely miswire or misunderstand three specific pins on the 555 timer. Here is how to avoid the most common bench failures.
Pin 5 (Control Voltage) connects directly to the internal resistive voltage divider. If left unconnected, it acts as an antenna for electromagnetic interference, causing erratic timing or spontaneous oscillation. The Fix: Always solder a 10nF (0.01µF) ceramic capacitor between Pin 5 and Pin 1 (GND). Even on CMOS variants where the datasheet calls it "optional," bench experience dictates it is mandatory in noisy environments.
Pin 7 (Discharge) vs. Pin 3 (Output)
A frequent mistake is using Pin 7 to drive a load like an LED or a relay. Pin 7 is an open-collector transistor connected to ground. It can sink current (pull to GND) but it cannot source current (push to VCC). If you connect an LED between VCC and Pin 7 with a current-limiting resistor, it will work, but the timing resistor network will interact with the LED current, ruining your duty cycle. The Fix: Always use Pin 3 (Output) to drive loads. Pin 3 is a totem-pole push-pull stage designed to source and sink up to 200mA on bipolar versions.
The Pin 4 (Reset) Ghost Trigger
Pin 4 is active low. If you leave it unconnected (floating), the high impedance of the pin will couple with stray capacitance and noise on the breadboard, randomly resetting your timer. The Fix: If your circuit does not require a reset function, run a direct jumper wire from Pin 4 to Pin 8 (VCC). Do not use a pull-up resistor; a direct hard-wired connection prevents voltage sag during transient spikes.
Schematic Symbols and Faded Chip Markings
While NEC and IEC color codes govern mains wiring and cable jackets, IC pinouts are governed by JEDEC package standards (for physical dimensions) and schematic symbol standards. When reading schematics, you will encounter two distinct regional/standard variants for drawing the 555 timer:
- ANSI/IEEE Std 91-1984 (US Standard): Depicts the 555 as a rectangular block with specific logic symbols inside (flip-flops, comparators, and inverters). Pin numbers are typically placed outside the rectangle.
- IEC 60617 (International/European Standard): Uses a similar rectangular block but employs different internal notation for the comparators and logic gates, often grouping pins by function rather than physical sequence.
Safe Interpretation When Markings are Faded or Missing
When salvaging parts or dealing with heavily used DIP-8 chips, the laser etching indicating the part number and Pin 1 dot may be completely worn off. Here is the decision path to safely identify orientation without guessing:
- Physical Indicators: Feel the top edge of the IC for the half-moon notch. Look closely at an angle under a bright light for a small circular dimple in the plastic near Pin 1.
- The Multimeter Diode Test (Bipolar NE555 only): If physical markers are sanded off, set your multimeter to diode-test mode. Place the red probe on a suspected Pin 1 and the black probe on the opposite corner (suspected Pin 8). Due to the internal VCC-to-GND protection diode, you will read a forward voltage drop of approximately 0.5V to 0.7V. If you read "OL" (open loop), reverse the probes or move to the next pin pair. This internal substrate diode is a reliable fingerprint for bipolar 555 timers.
Decision Tree: Bipolar vs. CMOS 555 Variants
The original Signetics NE555 was bipolar. Modern CMOS versions solved the bipolar chip's inherent flaws (high quiescent current and output crossover spikes) but introduced new limitations. Use this decision matrix to select the exact part number for your build.
| Application Requirement | Recommended Variant | Exact Part Number | Why This Wins |
|---|---|---|---|
| High current direct drive (relays, high-power LEDs) | Bipolar | Texas Instruments NE555P | Robust 200mA push-pull output stage; highly tolerant of inductive kickback and transient voltage spikes. |
| Low power battery operation (9V battery, solar) | CMOS | Texas Instruments TLC555 | Drops quiescent current from ~10mA to ~1mA. Eliminates the 400mA crossover current spike that drains batteries during output switching. |
| Low voltage logic (3.3V ESP32 GPIO, single Li-ion cell) | CMOS | Texas Instruments LMC555 | Operates reliably down to 2.0V VCC. Provides true rail-to-rail output, ensuring a 3.3V VCC yields a 3.3V logic high. |
When a bipolar NE555 switches its output (Pin 3) from high to low, both internal output transistors conduct simultaneously for a few nanoseconds. This creates a massive current spike (up to 400mA) drawn directly from VCC. If your VCC decoupling capacitor is placed too far away, this spike causes a localized brownout that can reset nearby microcontrollers. Always place a 100nF MLCC capacitor as physically close to Pins 1 and 8 as possible.
Real-World Bench Measurements and Edge Cases
Datasheets provide ideal conditions; the workbench provides reality. When debugging a 555 timer circuit, keep these measured edge cases in mind.
The Bipolar Output Voltage Drop
If you power a bipolar NE555 with a 5.0V supply and measure Pin 3 (Output) when high, you will not read 5.0V. You will read approximately 3.3V to 3.5V. This is due to the internal Darlington transistor pair and the voltage drop across the internal current-limiting resistor. If you are using the 555 to drive a 5V logic gate (like a 74HC series IC), this 3.5V high might be dangerously close to the logic threshold. The Fix: Use a CMOS variant (TLC555 or LMC555) for 5V logic interfacing, as their output will swing to within 50mV of the VCC rail.
Timing Capacitor ESR and Leakage
The timing accuracy of Pins 6 and 7 relies entirely on the external RC network. If your measured frequency or pulse width drifts significantly from your calculated values, the issue is rarely the 555 itself. It is almost always the capacitor. Electrolytic capacitors have high Equivalent Series Resistance (ESR) and significant leakage current. Because Pin 6 (Threshold) monitors voltage, capacitor leakage will artificially raise the voltage, causing the timer to reset prematurely. The Fix: For timing values under 1 second, use C0G/NP0 ceramic or polypropylene film capacitors. For longer delays where you must use electrolytics, derate the expected timing by 10-15% to account for leakage, or switch to a microcontroller-based timer.
For authoritative specifications and absolute maximum ratings, always consult the manufacturer datasheets, such as the Texas Instruments NE555 product page for bipolar limits, or the TLC555 datasheet for CMOS power characteristics. Understanding these physical and electrical realities ensures your 555 timer circuits trigger reliably every time.
