The 555 timer remains the most widely manufactured integrated circuit in history, but misinterpreting its pins or schematic symbols will instantly fry your prototype or cause erratic oscillation. Below is the definitive 555 timer IC pinout reference, covering physical DIP-8 layouts, schematic drafting standards, and the specific electrical traps that catch hobbyists and engineers alike.
The Standard 8-Pin DIP 555 Timer IC Pinout
Whether you are using the classic bipolar NE555, the low-power CMOS TLC555, or the automotive-grade NA555, the physical 8-pin Dual In-Line Package (DIP-8) pinout is universally standardized under JEDEC MS-001. Pin 1 is always identified by a half-moon notch at the top of the IC or a stamped dot next to the pin.
| Pin | Name | I/O | Internal Connection | Practical Function & Notes |
|---|---|---|---|---|
| 1 | GND | Power | Substrate / Ground Plane | Reference 0V. Must share a clean ground plane with your timing capacitor. |
| 2 | TRIG | Input | Inverting Comparator (-) | Falling below 1/3 VCC sets the internal flip-flop HIGH. High impedance. |
| 3 | OUT | Output | Totem-Pole / Push-Pull | Sources/sinks up to 200mA (bipolar). CMOS variants offer rail-to-rail output. |
| 4 | RESET | Input | Flip-Flop Clear | Active LOW. Overrides TRIG/THRES. Must be tied to VCC if unused. |
| 5 | CTRL | I/O | 2/3 VCC Divider Node | Access to the internal voltage divider. Requires a 10nF-100nF bypass cap to GND. |
| 6 | THRES | Input | Non-Inverting Comparator (+) | Rising above 2/3 VCC resets the flip-flop LOW. High impedance. |
| 7 | DISCH | Output | Open-Collector NPN | Sinks current to discharge the timing cap. Cannot source current. Max 200mA. |
| 8 | VCC | Power | Positive Supply Rail | 4.5V to 16V (bipolar), up to 18V absolute max. 2V to 15V for CMOS variants. |
Schematic Symbols and Packaging Standards
While NEC and IEC color codes govern mains wiring, the 555 timer operates under specific semiconductor and schematic drafting standards. If you are reading a schematic from a different region, the symbol for the 555 timer IC pinout will look different, even though the underlying circuit is identical.
IEEE 315 (US/Standard) vs. IEC 60617 (European)
- IEEE 315 (ANSI/Y32.2): Predominant in North America and most global datasheets (like those from Texas Instruments). The 555 is drawn as a simple rectangular box with pin numbers written on the outside and basic labels (TRIG, THRES, OUT) on the inside. Internal logic gates are rarely drawn.
- IEC 60617: Standard in European technical documentation. The 555 is often drawn as a rectangular block featuring standardized internal logic notation. You will see IEC-standard logic symbols inside the box, such as
&for AND gates,≥1for OR gates, and specific qualifying symbols for the comparators and SR latch. Pin numbers are still placed outside the boundary.
The Rows People Get Wrong: Critical Pinout Mistakes
When debugging a 555 circuit on the bench, 90% of failures trace back to three specific pins being misused or left floating.
Pin 5 (CTRL): The Floating Noise Antenna
Pin 5 taps directly into the midpoint of the internal 5kΩ-5kΩ-5kΩ resistor ladder that sets the comparator thresholds. Because these resistors are relatively high value, Pin 5 acts as a high-impedance antenna. If left floating, it will couple high-frequency switching noise from the output stage back into the threshold comparators, causing severe timing jitter. Fix: Always place a 10nF to 100nF ceramic decoupling capacitor between Pin 5 and Pin 1 (GND), placed as physically close to the IC as possible.
Pin 7 (DISCH): The Open-Collector Trap
Beginners frequently try to use Pin 7 to drive an LED or relay directly HIGH. Pin 7 is an open-collector NPN transistor. It can sink up to 200mA to ground (pulling low), but it has absolutely no internal connection to VCC to source current (pulling high). If you need to drive a load high, you must use Pin 3 (OUT), or use Pin 7 to pull down an external pull-up resistor.
Pin 4 (RESET): The Weak Internal Pull-Up
Pin 4 is active LOW. While some modern CMOS variants (like the LMC555) have a weak internal pull-up resistor on the reset pin, the classic bipolar NE555 does not guarantee a reliable internal pull-up. If left unconnected, stray capacitance or noise can momentarily pull the pin low, resetting your timer mid-cycle. Fix: Always tie Pin 4 directly to Pin 8 (VCC) with a jumper wire if you are not using an external reset switch.
Identifying Pins on Faded, Cloned, or SMD Variants
When working with salvaged parts, cheap unbranded clones, or Surface Mount Device (SMD) variants like the SOIC-8 TLC555, physical markings are often sanded off, faded, or entirely missing. Here is how to safely interpret the 555 timer IC pinout when visual cues fail.
- The Substrate Diode Test (Bipolar NE555 only): Set your multimeter to diode test mode. Place the red probe on Pin 1 (assumed GND) and the black probe on Pin 8 (assumed VCC). You should read a specific forward voltage drop (typically around 0.6V to 0.8V) due to the internal substrate protection diodes. Reversing the probes should read 'OL' (open loop). If you get a short or no reading, your assumed Pin 1/8 orientation is flipped.
- SMD Dot Identification: On SOIC-8 and TSSOP-8 packages, the half-moon notch is replaced by a tiny laser-etched or molded dot. This dot always designates Pin 1. Count counterclockwise around the chip to map the remaining pins.
- CMOS vs Bipolar Continuity: If you need to determine if an unmarked chip is a bipolar NE555 or a CMOS ICM7555/TLC555, measure the resistance between VCC and GND (unpowered). Bipolar chips will show a lower resistance (often a few kilo-ohms) due to the internal resistor ladder and biasing networks, while CMOS chips will read near open-circuit (Mega-ohms) until the internal gate capacitances charge.
555 Timer IC Pinout FAQ
Are the CMOS (LMC555/TLC555) and Bipolar (NE555) 555 timer IC pinouts identical?
Yes, they are 100% pin-for-pin compatible in a DIP-8 or SOIC-8 package. However, their electrical behavior on those pins differs drastically. The classic bipolar NE555 output (Pin 3) cannot reach the positive rail; it drops about 1.5V to 2V below VCC due to the internal Darlington transistor pair. If you are running a 12V supply, Pin 3 will only output ~10.5V. The CMOS TLC555 or LMC555 features a true rail-to-rail push-pull output stage on Pin 3, but it can only source/sink about 10mA to 100mA compared to the bipolar's 200mA. Furthermore, CMOS variants draw microamps of quiescent current, while the bipolar NE555 draws several milliamps just sitting idle.
Why does my 555 timer IC pinout not match the datasheet when I look at the bottom of the chip?
If you are looking at the bottom of the IC (the side with the metal legs facing up), the pin numbering is mirrored. The stamped dot or notch indicates Pin 1, but when viewed from the bottom, the pins count clockwise rather than counterclockwise. Always read the 555 timer IC pinout from the top down, with the legs pointing away from you or into the breadboard. For the official mechanical dimensions and orientation markers, refer to the Texas Instruments NE555 Datasheet packaging section.
Can I use Pin 7 (DISCH) and Pin 3 (OUT) interchangeably to drive a relay?
No. While both pins switch low at the exact same time (they are tied to the same internal flip-flop state), Pin 3 is a totem-pole output that actively drives both HIGH and LOW. Pin 7 is an open-collector discharge transistor. If you connect a relay coil between VCC and Pin 7, it will pull the relay to ground when active, but when it turns off, the relay coil has no path to discharge its inductive kickback, which will generate a massive voltage spike that can destroy the internal NPN transistor. Always use Pin 3 for driving relays, and always include a reverse-biased flyback diode across the relay coil.
