The 555 timer is the most widely used integrated circuit in electronics history. Whether you are building an astable multivibrator for a PWM motor controller or a monostable delay circuit for a relay, the physical pinout remains identical across almost all modern variants. Below is the definitive reference for the standard 8-pin configuration, followed by schematic symbol standards and the most common bench mistakes.
The Standard 8-Pin 555 Timer Pinout Table
The following table applies to the ubiquitous DIP-8 (through-hole) and SOIC-8 (surface-mount) packages. Pin numbering always begins at the top-left (closest to the orientation notch or dot) and proceeds counter-clockwise.
| Pin | Name | Function in Practice | Internal Connection |
|---|---|---|---|
| 1 | Ground (GND) | Connects to the circuit's 0V reference. Must handle the return current for both the internal logic and the output stage. | Substrate / Common ground plane. |
| 2 | Trigger (TRIG) | Starts the timing cycle. When pulled below 1/3 VCC, the output (Pin 3) goes HIGH. | Inverting input of the lower internal comparator. |
| 3 | Output (OUT) | Push-pull totem-pole output. Can source or sink up to 200mA (bipolar) to drive relays, LEDs, or small motors directly. | Output stage driver transistors. |
| 4 | Reset (RST) | Active-LOW override. Pulling this below 0.7V forces the output LOW, regardless of Trigger or Threshold states. | Base of the internal reset transistor. |
| 5 | Control Voltage (CTRL) | Provides direct access to the internal voltage divider. Used for PWM modulation or frequency shifting. | Non-inverting input of the upper comparator (tied to the 2/3 VCC divider node). |
| 6 | Threshold (THRES) | Ends the timing cycle. When voltage rises above 2/3 VCC, the output (Pin 3) goes LOW. | Non-inverting input of the upper internal comparator. |
| 7 | Discharge (DISCH) | Open-collector NPN transistor. Sinks current to ground to discharge the external timing capacitor. | Collector of the internal discharge transistor. |
| 8 | Supply (VCC) | Positive power rail. Rated for 4.5V to 16V on bipolar (NE555) and 1.5V to 15V on CMOS (LMC555) variants. | Positive supply node for internal biasing and output stage. |
Schematic Symbols and Package Variants (ANSI vs. IEC)
While the NEC governs mains wiring colors and conduit fill in North America, it does not apply to IC schematic symbols. Instead, the way a 555 timer is drawn on a schematic depends on your regional engineering standards.
ANSI/IEEE Std 91 (North America): The modern US standard dictates a rectangular outline for the 555 timer. Inside the box, specific logic qualifiers (like 'TRIG' with a small circle indicating active-low, or 'DISCH' with an open-collector symbol) are used. If you are reading a schematic from a US university or a modern Texas Instruments datasheet, you will see this rectangular block.
IEC 60617 (Europe, UK, and Global): The international standard also uses a rectangular boundary but relies heavily on standardized internal logic symbols rather than text labels. The trigger and threshold inputs will feature specific IEC comparator qualifiers. Most modern EU-based CAD libraries (like Altium or KiCad default EU sets) use this format.
Legacy / Old UK & US Hobbyist Symbols: In older literature (pre-1990s) and many modern hobbyist blogs, the 555 is drawn as a simple triangle (resembling an op-amp) or a generic box with just the pin numbers 1-8 written on the outside. Warning: Never rely on legacy triangle symbols for professional board layout, as they often omit the internal open-collector nature of Pin 7, leading to catastrophic design errors when sourcing current.
Package Variants: The pinout table above applies universally to the DIP-8 (Dual In-line Package, 0.1" pitch) and SOIC-8 (Small Outline IC, 0.05" pitch). For ultra-compact designs, the VSSOP-8 (Very Thin Shrink Small Outline Package) uses the exact same logical pinout, though the physical pitch shrinks to 0.65mm, requiring a reflow oven or hot-air station for assembly.
Common Pinout Mistakes and Faded IC Identification
Even experienced engineers make specific errors when wiring the 555 timer. Here are the rows from the table above that cause the most bench failures.
Pin 4 is active-LOW. If you leave it unconnected (floating) on a breadboard, electromagnetic noise or static buildup can pull the pin below the 0.7V threshold, instantly killing your output signal. Always tie Pin 4 directly to VCC (Pin 8) if you are not using an external reset switch.
The Missing Bypass Capacitor on Pin 5: Pin 5 (Control Voltage) taps directly into the internal 5kΩ resistor ladder that sets the 2/3 VCC threshold. Because it is high-impedance, it acts as an antenna for high-frequency noise. If you do not need to modulate the control voltage, you must connect a 10nF to 100nF ceramic capacitor between Pin 5 and Pin 1 (Ground). Without it, your timing intervals will jitter wildly, especially near switching power supplies or motors.
Confusing Pin 7 (Discharge) with Pin 3 (Output): Pin 3 is a push-pull output that can both source (provide) and sink (absorb) up to 200mA. Pin 7 is an open-collector NPN transistor. It can sink current to ground (pulling a node LOW), but it cannot source current. If you try to use Pin 7 to drive an LED directly to ground without a pull-up resistor to VCC, the LED will never illuminate.
Safe Interpretation When Markings are Faded or Missing
When salvaging vintage Signetics or early TI NE555N chips, the laser etching or painted Pin 1 indicator dot is often completely worn away. Do not guess the orientation; applying reverse polarity (VCC to Pin 1, GND to Pin 8) will instantly destroy the internal silicon die via thermal runaway.
The Multimeter Ground-Plane Test: If the physical notch is also sanded off, insert the IC into your unpowered breadboard. Set your multimeter to continuity mode. Probe the large ground pour or the negative rail of your power supply. Probe the pins on one side of the IC. Pin 1 is almost universally routed to the main ground plane in standard astable and monostable layouts. Once you confirm which pin shows 0.1Ω to your main ground rail, you have identified Pin 1. Verify by checking the opposite corner pin for continuity to your positive rail (Pin 8).
555 Timer Pinout FAQs
What is the difference between NE555 and LMC555 pinouts?
The physical 8-pin layout is 100% identical, but the internal silicon dictates how you use the pins. The NE555 is a bipolar junction transistor (BJT) design. It draws roughly 10mA of quiescent current just sitting idle, and its output stage has a voltage drop of about 1.5V to 2V below VCC when driving high. The LMC555 (and TLC555) are CMOS designs. They draw less than 150µA of quiescent current and feature rail-to-rail output swings. However, the CMOS Pin 7 (Discharge) has a much higher 'on' resistance (often 10Ω to 50Ω compared to the bipolar's ~10Ω). If you swap an NE555 for an LMC555 in an existing astable circuit without recalculating your timing resistors, your discharge time will skew, altering your duty cycle. For a deep dive into the CMOS internal architecture, refer to the Texas Instruments LMC555 datasheet.
How do I wire a 555 timer in astable mode using this pinout?
For a standard free-running oscillator (astable mode), wire the pins as follows:
Power: Pin 1 to GND, Pin 8 to VCC (e.g., 9V). Tie Pin 4 to Pin 8.
Timing Network: Connect Resistor A (R1) between Pin 8 and Pin 7. Connect Resistor B (R2) between Pin 7 and Pin 6. Connect your timing capacitor (C1) between Pin 6 and Pin 1 (GND).
Feedback: Jumper Pin 6 (Threshold) directly to Pin 2 (Trigger).
Stability: Place a 10nF capacitor between Pin 5 and Pin 1.
Output: Take your square wave signal from Pin 3. The frequency is determined by the formula: f = 1.44 / ((R1 + 2*R2) * C1). You can verify these calculations using standard tools like the All About Circuits 555 Astable Calculator.
Why is my 555 timer outputting a constant high or low signal?
If your Pin 3 output is stuck, check the comparator inputs first. If the output is stuck HIGH, measure Pin 2 (Trigger). If the voltage on Pin 2 is being held below 1/3 of your VCC supply, the lower comparator is continuously triggering the flip-flop. Ensure your trigger switch or sensor is actually releasing and pulling the pin back up to VCC via a pull-up resistor.
If the output is stuck LOW, check two pins. First, measure Pin 4 (Reset). If it is below 0.7V, the chip is being held in reset. Second, measure Pin 6 (Threshold). If the voltage on Pin 6 is stuck above 2/3 VCC (often caused by a shorted timing capacitor or an incorrectly sized R2 resistor that cannot discharge the cap fast enough), the upper comparator will force the output low and keep Pin 7 (Discharge) permanently grounded.
