A 4-to-1 multiplexer (MUX) acts as a digitally controlled 4-position rotary switch. It routes one of four digital data inputs to a single output based on the state of two select lines. While you can buy dedicated MUX ICs like the 74HC153, building a 4 to 1 multiplexer circuit diagram from discrete logic gates is a foundational bench exercise. It forces you to confront propagation delays, fan-out limits, and floating-input hazards that are hidden inside monolithic silicon.
This guide walks through the discrete AND-OR topology, provides a dynamic behavior table, and details exactly how to breadboard, test, and troubleshoot the circuit using standard 74HC-series logic.
The Discrete Logic Topology and Node Labels
The most robust way to build a digital 4:1 MUX on a breadboard is using a two-level Sum-of-Products (AND-OR) topology. This architecture guarantees full logic-level restoration, meaning a degraded or noisy input signal is squared up into a clean digital output.
The circuit requires three types of gates, mapped to specific node labels:
- Select Nodes ($S_0, S_1$): The two control inputs. These feed into a dual inverter (74HC04) to generate the complementary nodes $\overline{S_0}$ and $\overline{S_1}$.
- Data Nodes ($D_0, D_1, D_2, D_3$): The four payload inputs.
- Internal Product Nodes ($P_0$ to $P_3$): The outputs of four 3-input AND gates (74HC11).
- $P_0 = \overline{S_1} \cdot \overline{S_0} \cdot D_0$
- $P_1 = \overline{S_1} \cdot S_0 \cdot D_1$
- $P_2 = S_1 \cdot \overline{S_0} \cdot D_2$
- $P_3 = S_1 \cdot S_0 \cdot D_3$
- Output Node ($Y$): The final sum node, generated by feeding $P_0$ through $P_3$ into a 4-input OR gate (74HC4072).
State Behavior and Switching Dynamics
Standard truth tables only show static states. To actually understand how a 4 to 1 multiplexer circuit diagram behaves in real time, you need to know what happens to the output node $Y$ when specific elements change state. The table below maps the active logic path and isolates the effect of toggling selected versus unselected data lines.
| $S_1$ | $S_0$ | Active AND Gate | Selected Data Node | Effect on $Y$ when Selected $D$ Toggles | Effect on $Y$ when Unselected $D$ Toggles |
|---|---|---|---|---|---|
| 0 | 0 | $P_0$ (Gate 0) | $D_0$ | $Y$ follows $D_0$ exactly (in-phase) | No change ($Y$ remains locked to $D_0$) |
| 0 | 1 | $P_1$ (Gate 1) | $D_1$ | $Y$ follows $D_1$ exactly (in-phase) | No change ($Y$ remains locked to $D_1$) |
| 1 | 0 | $P_2$ (Gate 2) | $D_2$ | $Y$ follows $D_2$ exactly (in-phase) | No change ($Y$ remains locked to $D_2$) |
| 1 | 1 | $P_3$ (Gate 3) | $D_3$ | $Y$ follows $D_3$ exactly (in-phase) | No change ($Y$ remains locked to $D_3$) |
Reference: For a deeper look at how propagation delay skews these transitions during select-line changes, consult the NXP 74HC153 datasheet, which details the internal timing diagrams of monolithic equivalents.
AND-OR Logic vs. CMOS Transmission Gates
Why build a 4 to 1 multiplexer circuit diagram using discrete AND-OR gates when you could use a CMOS analog switch like the CD4052 or the transmission-gate topology found inside ASICs?
The choice comes down to signal restoration versus signal transparency.
- AND-OR Topology (Discrete 74HC): This is a purely digital implementation. If your $D_0$ input is a noisy, slow-rising analog waveform that crosses the logic threshold multiple times, the AND gate will interpret it as a clean digital HIGH or LOW. The output $Y$ will have crisp, rail-to-rail edges. The trade-off is propagation delay; a signal passing through an inverter, an AND gate, and an OR gate will accumulate roughly 45ns to 60ns of delay at 5V.
- Transmission Gate Topology (CMOS Pass-Transistor): This acts as a physical resistor connecting the input to the output. It passes both digital and analog signals (like audio or sensor voltages). However, it provides zero signal restoration. If the input is noisy, the output is noisy. Furthermore, the $R_{ON}$ (on-resistance) of the pass transistor creates a voltage divider with your load, meaning you lose signal amplitude.
Component Selection and Extreme Failure Modes
To build this on a breadboard, you need specific ICs and passive support components. Here is the exact bill of materials and the design values required to keep the circuit stable.
Real Component Values
- U1 (Inverters): 74HC04 Hex Inverter. Used to generate $\overline{S_0}$ and $\overline{S_1}$.
- U2 (AND Gates): 74HC11 Triple 3-Input AND. (You will need two of these ICs, or one 74HC11 and one 74HC21 dual 4-input AND configured as 3-input).
- U3 (OR Gate): 74HC4072 Dual 4-Input OR.
- Select Line Biasing: 10 kΩ pull-down resistors on $S_0$ and $S_1$.
- Decoupling: 100 nF (0.1 µF) X7R MLCC capacitors placed physically adjacent to the VCC/GND pins of every single IC.
What Breaks at the Extremes?
When debugging a multiplexer, failures usually happen at the physical extremes of the circuit. Here is what breaks and why:
- Open/Floating Select Lines: If you forget the 10 kΩ pull-down resistors and leave $S_0$ or $S_1$ unconnected, the high-impedance CMOS inputs will pick up ambient electromagnetic noise. The MUX will rapidly oscillate between all four data channels. This causes 'shoot-through' current inside the ICs, leading to excessive heat and a completely garbled output on $Y$.
- Shorted Output Node ($Y$ to GND): If you accidentally short the output pin of the 74HC4072 to ground while the active AND gate is outputting a HIGH, the internal PMOS pull-up transistor will attempt to source infinite current. It will hit the absolute maximum rating of ~25 mA and likely melt the internal silicon bond wire, permanently destroying the OR gate IC.
- Exceeding Fan-Out: If you connect the $Y$ output to more than 10 standard 74HC inputs, the capacitive load will slow down the edge transition times, increasing propagation delay and potentially causing timing violations in downstream synchronous circuits.
Step-by-Step Breadboard Verification
Do not wire the entire 4 to 1 multiplexer circuit diagram at once and expect it to work. Build and test in stages to isolate faults.
- Power and Decouple: Insert the 74HC04, 74HC11, and 74HC4072 ICs across the breadboard center trench. Wire VCC (Pin 14) and GND (Pin 7) for all ICs. Install the 100 nF decoupling capacitors immediately. Power on and verify 5V at the furthest IC.
- Verify the Inverters: Wire a toggle switch to the input of one 74HC04 inverter. Use a multimeter or logic probe on the output. Verify that a 0V input yields ~5V, and a 5V input yields ~0V. This confirms your power rails and basic IC health.
- Test a Single AND Path: Wire only the $P_0$ path. Connect $S_1$ and $S_0$ to GND (via your 10 kΩ pull-downs). Connect $D_0$ to a toggle switch. Probe the output of the 74HC11 AND gate. It should only go HIGH when $D_0$ is HIGH. If it stays HIGH, check for a missing ground connection on the unused inputs of the 74HC11 package (unused CMOS inputs must be tied to VCC or GND).
- Integrate the OR Gate: Connect the outputs of your AND gates to the 74HC4072. Tie $D_1, D_2$, and $D_3$ to GND. Toggle $D_0$ and cycle through all four combinations of $S_1$ and $S_0$. The output $Y$ should only mirror $D_0$ when $S_1=0, S_0=0$.
- Dynamic Scope Test: For the final validation, disconnect the $D_2$ toggle switch and connect a function generator set to a 10 kHz, 0-5V square wave. Set $S_1=1, S_0=0$. Probe $Y$ with an oscilloscope. You should see a clean 10 kHz square wave. Measure the propagation delay from the function generator trigger to the $Y$ edge; it should read between 40 ns and 70 ns depending on your specific IC manufacturer and breadboard capacitance.
By following this staged verification, you isolate wiring errors to specific logic levels rather than chasing a ghost through 30 overlapping jumper wires. For further reading on standardizing your logic bench setups, the Texas Instruments Logic Family Application Report provides excellent baseline data on input thresholds and drive capabilities across the HC and HCT families.
