A 4-bit binary sequence—commonly called a nibble—contains exactly 16 possible states, ranging from 0000 to 1111. In digital electronics, microcontrollers, and logic ICs, these four bits form the foundational building block for everything from memory addressing to 7-segment display decoding. The direct answer to how many values a 4-bit system holds is 16 (decimal 0 through 15). However, how you interpret those four bits depends entirely on the data format your circuit or code requires.

The Master 4-Bit Binary Reference Chart

This table maps every possible 4-bit state across the most common digital logic representations. Standardized under foundational digital logic principles (such as those outlined in All About Circuits' digital textbook and standard IEC/IEEE logic family datasheets), this chart is your bench-side reference for debugging shift registers, counters, and GPIO ports.

How to read this table: The Binary column shows the raw high/low (1/0) states of your logic pins, where the leftmost bit is the Most Significant Bit (MSB, weight of 8) and the rightmost is the Least Significant Bit (LSB, weight of 1). The Decimal column is the standard unsigned base-10 value. Hex is the base-16 shorthand used in C/C++ code. BCD (8421) maps binary to decimal digits for displays, and Two's Comp shows the signed integer value used in math operations.
Binary (MSB→LSB) Decimal (Unsigned) Hexadecimal Octal BCD (8421) Two's Complement (Signed)
000000x0000
000110x1111
001020x2222
001130x3333
010040x4444
010150x5555
011060x6666
011170x7777
100080x8108-8
100190x9119-7
1010100xA12Invalid-6
1011110xB13Invalid-5
1100120xC14Invalid-4
1101130xD15Invalid-3
1110140xE16Invalid-2
1111150xF17Invalid-1

Bookmark-Friendly Quick-Jump Notes

  • 0000 (Zero / Reset): The default state of a cleared shift register or an unasserted GPIO port. All lines low.
  • 0111 (Max Positive Signed): The highest positive value in a signed 4-bit Two's Complement system before the MSB flips the sign.
  • 1000 (Sign Bit / BCD 8): The exact boundary where unsigned decimal crosses into negative signed territory. In BCD, this is the highest valid tens-digit weight.
  • 1010 (Hex A / Invalid BCD): The first state that breaks Binary-Coded Decimal. If you see this on a CD4511 BCD-to-7-segment decoder, the display will typically go blank.
  • 1111 (Max Unsigned / -1 Signed): All lines high. Represents 15 in unsigned logic, but -1 in Two's Complement math.

Which Column Applies to Your Circuit or Code?

Knowing the table is only half the battle; applying the correct column to your specific hardware is where bench mistakes happen. Here is how to determine which representation your installation actually uses.

Use Hexadecimal (0x0 - 0xF) for Microcontrollers and Memory. When writing firmware for an ESP32 or Arduino, you are manipulating hardware registers. If you need to set the top four bits of an 8-bit port high and the bottom four low, you write 0xF0. Thinking in binary (11110000) is prone to counting errors on the bench, while decimal (240) obscures the bitwise boundaries. Hexadecimal perfectly maps to the 4-bit nibble, making it the mandatory standard for embedded C/C++ bitmasking.

Use BCD (8421) for Digital Displays and RTCs. If you are wiring a CD4511 BCD-to-Latch/Decoder to drive a 7-segment display, or reading a DS3231 Real-Time Clock via I2C, the hardware expects Binary-Coded Decimal. In BCD, each 4-bit nibble represents a single decimal digit (0-9). The states from 1010 to 1111 are strictly forbidden. If your microcontroller accidentally sends 0xB to a CD4511, the decoder enters an invalid state and blanks the display to prevent ambiguous readings.

Use Two's Complement for Sensor Math and DSP. When reading raw data from an I2C accelerometer (like the MPU6050) or performing digital signal processing, negative numbers are required. Hardware doesn't have a "minus sign" pin. Instead, it uses the MSB as a sign indicator. If your logic analyzer shows 1101 on the data bus, and the sensor outputs signed 4-bit (or scaled 4-bit) data, that value is -3, not 13.

How Signed Math and BCD Modify the Base Value

In wire sizing, ambient temperature derating modifies the base ampacity of a conductor, reducing its safe current limit. In digital logic, format constraints similarly modify the usable base value of a 4-bit register, effectively "derating" the maximum positive number you can represent.

The Two's Complement Derating: In a standard unsigned 4-bit system, your range is 0 to 15. But if your application requires negative numbers (e.g., a motor controller handling forward and reverse PWM values), you must use Two's Complement. This format modifies the base value by assigning a negative weight to the MSB. Instead of the leftmost bit being worth +8, it becomes -8. Consequently, your maximum positive value is "derated" from 15 down to 7 (0111). Any binary sequence starting with a 1 is now a negative number, shrinking your positive headroom by half.

The BCD Derating: Binary-Coded Decimal modifies the base value by entirely amputating the top six states. Because BCD only maps to human-readable decimal digits (0-9), the binary states representing 10 through 15 (1010 through 1111) are invalid. If you are designing a counter circuit using a 74LS93 4-bit binary counter (reference the Texas Instruments SN74LS93 datasheet), the chip will naturally count up to 15. If you feed that directly into a BCD decoder without a modulo-10 reset circuit to force the counter back to zero at 1010, your display will glitch through six invalid states on every cycle.

What This Table Cannot Tell You (Hardware Realities)

A reference chart gives you the mathematical truth, but it cannot predict how those 1s and 0s behave in physical silicon. When debugging a circuit, keep these hardware realities in mind:

  • Propagation Delay and Metastability: The table implies that a counter transitions from 0111 (7) to 1000 (8) instantaneously. In reality, physical logic gates have propagation delays (often 10ns to 50ns in standard 74HC series logic). During the transition from 0111 to 1000, all four bits must flip. Due to microscopic differences in gate switching speeds, the circuit may briefly pass through intermediate states like 0000 or 1111. If you are using these bits to trigger edge-sensitive interrupts, this "glitching" will cause false triggers. Always use Gray code or hardware synchronization when sampling asynchronous 4-bit buses.
  • Voltage Thresholds (TTL vs. CMOS): The table defines a 1 and a 0, but not the voltage required to achieve them. If you are interfacing a 5V 74LS (TTL) logic chip with a 3.3V ESP32, you must check the $V_{IH}$ (Input High Voltage) threshold. Standard TTL requires roughly 2.0V to register a "1", which a 3.3V MCU can drive. However, if you use a 74HC (CMOS) chip powered at 5V, it requires roughly 3.5V to register a "1". The 3.3V output from your ESP32 will be read as a "0", causing your binary sequence to fail silently. Always match logic families or use a level shifter like the TXB0104.
  • Switch Bounce: If your 4 bits are coming from mechanical DIP switches or a rotary encoder, the table assumes clean transitions. Physical contacts bounce for milliseconds, generating dozens of rapid 1-to-0-to-1 transitions. A microcontroller polling the pins at 10kHz will read a single switch flip as a chaotic spray of binary values. You must implement RC debounce circuits (e.g., a 10kΩ resistor and 0.1µF capacitor) or software debouncing to ensure the hardware actually matches the theoretical table.

For deeper study on binary logic families and mathematical conversions, refer to the foundational guides at Electronics Tutorials. Keep this 4 bit binary number table bookmarked for your next logic analyzer session or firmware bitmasking task.