The 3 input NAND gate symbol represents a logic gate that outputs a LOW (0) state only when all three of its inputs are simultaneously HIGH (1). In the US (ANSI/IEEE 315 standard), it is drawn as a D-shaped AND gate with an inversion bubble on the output. In Europe and internationally (IEC 60617), it is drawn as a rectangular box with an & qualifier and an output bubble. For practical bench work, the most common physical implementation is a 14-pin DIP IC containing three independent 3-input NAND gates, such as the 74HC10 or CD4023.
Symbol Standards and Truth Table Reference
Before wiring a circuit, you must know which schematic standard your reference material uses. Misinterpreting the symbol shape can lead to wiring the wrong logic function. Below is the complete reference for the 3 input NAND gate symbol across regional standards, followed by the definitive truth table.
| Standard | Region / Authority | Visual Symbol Description | Key Identifier |
|---|---|---|---|
| ANSI/IEEE 315 | United States, Canada | D-shaped body (flat left, curved right) with a small circle (bubble) on the output line. | Curved right edge + inversion bubble |
| IEC 60617 | Europe, UK, International | Rectangular box with an & symbol inside and a small circle on the output line. |
Rectangle + & + inversion bubble |
| DIN 40700 (Legacy) | Older German/EU schematics | Rectangular box with a & and a small o or circle on the output. |
Largely superseded by IEC 60617 |
The 3-Input NAND Truth Table
Regardless of the symbol used on the schematic, the silicon behavior is identical. The output is the logical inverse of a 3-input AND gate.
| Input A | Input B | Input C | Output Y | Logic State |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | HIGH |
| 0 | 0 | 1 | 1 | HIGH |
| 0 | 1 | 0 | 1 | HIGH |
| 0 | 1 | 1 | 1 | HIGH |
| 1 | 0 | 0 | 1 | HIGH |
| 1 | 0 | 1 | 1 | HIGH |
| 1 | 1 | 0 | 1 | HIGH |
| 1 | 1 | 1 | 0 | LOW |
Standard 14-Pin DIP Pinout and IC Variants
The industry-standard package for 3-input NAND gates is the 14-pin Dual In-line Package (DIP). This package contains three independent gates. You can find this pinout in the Texas Instruments SN74HC10 Product Page and equivalent CMOS datasheets.
| Pin Number | Function | Gate Assignment | Notes |
|---|---|---|---|
| 1 | Input A1 | Gate 1 | Logic input |
| 2 | Input B1 | Gate 1 | Logic input |
| 3 | Input C1 | Gate 1 | Logic input |
| 4 | Output Y1 | Gate 1 | Logic output |
| 5 | Input A2 | Gate 2 | Logic input |
| 6 | Input B2 | Gate 2 | Logic input |
| 7 | GND | Power | 0V Reference |
| 8 | Output Y2 | Gate 2 | Logic output |
| 9 | Input C2 | Gate 2 | Logic input |
| 10 | Input A3 | Gate 3 | Logic input |
| 11 | Input B3 | Gate 3 | Logic input |
| 12 | Output Y3 | Gate 3 | Logic output |
| 13 | Input C3 | Gate 3 | Logic input |
| 14 | VCC | Power | Positive supply (2V-6V for HC, 3V-15V for 4000 series) |
Symbols and Pinout Rows People Get Wrong
Even experienced makers make specific mistakes when reading schematics or wiring DIP chips on a breadboard. Here are the most common errors and how to avoid them.
The most frequent cause of a "dead" or erratic NAND gate on the bench is leaving an unused input pin floating. On CMOS ICs (like the 74HC10 or CD4023), a floating input acts as an antenna, picking up ambient EMI. This causes the internal MOSFETs to oscillate at high frequencies, drawing massive current and overheating the die. Always tie unused inputs to VCC or GND.
- Confusing the IEC
&for an AND gate: In the IEC standard, the&inside the rectangle simply means "AND logic". The inversion bubble on the output line is what makes it a NAND. If you miss the bubble because of a faint schematic print, you will wire the circuit expecting an AND function and get inverted results. - Misidentifying Pin 1: On a 14-pin DIP, Pin 1 is always to the left of the half-moon notch (or the chamfered corner) when the IC text is facing up and readable. Pin 7 is bottom-left, Pin 8 is bottom-right. Counting from the wrong side reverses your entire pinout.
- Assuming TTL and CMOS are interchangeable without pull-ups: If you are driving a 74LS10 (TTL) input from a CMOS output, it usually works. But driving a CMOS input from an older TTL output can fail because TTL "HIGH" (approx 2.4V) might not meet the CMOS "HIGH" threshold (approx 3.5V at 5V VCC). Use a 10kΩ pull-up resistor on the TTL output if interfacing with HC-series CMOS.
Decision Path: Choosing Your 3-Input NAND IC
Do not just grab any 14-pin NAND chip from your parts bin. The right choice depends on your supply voltage, speed requirements, and environment. Use this decision tree to select the exact part number for your BOM.
| Your Circuit Condition | Required Action / Constraint | Concrete IC Pick |
|---|---|---|
| Standard 5V logic, moderate speed, modern design | Need low power consumption, wide 2V-6V operating range, and standard through-hole DIP. | 74HC10 (or 74HCT10 if interfacing with legacy 5V TTL) |
| Battery powered, wide voltage (9V, 12V, or unregulated) | Must operate reliably from 3V up to 15V without a voltage regulator. | CD4023B (CMOS 4000 series) |
| Repairing legacy 1980s/90s 5V TTL equipment | Must match original propagation delays and input current sinking characteristics. | 74LS10 (Low-power Schottky TTL) |
| High-speed data bus, 3.3V microcontroller logic | Need fast edge rates and 3.3V native operation without level shifting. | 74LVC10 (Low-voltage CMOS, surface mount usually required) |
Default Recommendation: If you are building a new hobbyist project, Arduino shield, or general-purpose logic circuit on a breadboard, buy the 74HC10. It is the most versatile, widely available, and forgiving IC for 5V and 3.3V systems. You can verify current stock and pricing via the Texas Instruments logic portal or major distributors like Mouser and DigiKey.
Bench Identification: Interpreting Faded or Missing Markings
When scavenging parts or troubleshooting a damaged PCB, you will occasionally encounter a 14-pin DIP with laser markings that are entirely faded, painted over, or scratched off. Here is the safe, systematic procedure to verify if a mystery chip is a 3-input NAND gate without relying on the silkscreen.
- Locate VCC and GND: Assume standard 14-pin logic pinout. Apply 5.0V DC to Pin 14 (VCC) and connect Pin 7 to your bench supply ground. Use a current-limited supply set to 50mA. If the chip draws more than 10mA with all inputs tied to GND, it is likely damaged or not a standard logic gate.
- Prepare the Inputs: Take Gate 1 (Pins 1, 2, and 3). Tie all three inputs to GND (Logic 0).
- Measure the Output: Use your multimeter to measure Pin 4 (Output Y1). It should read close to VCC (approx 4.9V to 5.0V for CMOS, slightly lower for TTL). This confirms the "0,0,0 = 1" truth table row.
- Test the Critical State: Move all three inputs (Pins 1, 2, 3) to VCC (Logic 1). Measure Pin 4 again. The voltage must drop to near 0V (Logic 0).
- Verify Asymmetry: Tie two inputs to VCC and one to GND. The output must return to HIGH. If the output only goes LOW when all three are HIGH, you have successfully identified a 3-input NAND gate.
