If you need to smooth a 5kHz PWM signal from a microcontroller into a clean DC voltage, a cascaded 2nd-order RC capacitor circuit diagram using 1 kΩ resistors and 1 µF capacitors yields a -3dB cutoff of ~159 Hz. This topology attenuates the 5kHz switching ripple by over -40 dB while keeping the output impedance low enough to drive an ADC or op-amp buffer without loading down the GPIO pin.
Topology Map and Real Component Selection
A single-stage (1st-order) RC filter only rolls off at -20 dB per decade. For a 5kHz PWM signal, a 1st-order filter with a 159 Hz cutoff only attenuates the fundamental ripple by about -30 dB, leaving visible sawtooth ripple on your oscilloscope. By cascading two identical RC stages, we achieve a 2nd-order response (-40 dB/decade), crushing the ripple to negligible levels.
Here is the node map for our cascaded capacitor circuit diagram:
- Vin: PWM source (e.g., ESP32 GPIO 25, 3.3V logic, 5kHz frequency).
- R1: 1 kΩ resistor (0805 or 1/4W through-hole).
- Node_A: Junction between R1, C1, and R2.
- C1: 1 µF ceramic capacitor (X7R dielectric) tied from Node_A to GND.
- R2: 1 kΩ resistor.
- Node_B: Junction between R2, C2, and Vout.
- C2: 1 µF ceramic capacitor (X7R dielectric) tied from Node_B to GND.
- Vout: Smoothed analog DC output.
Why these values? The ESP32 GPIO pins have an absolute maximum current rating of 40 mA, but a recommended continuous limit of 20 mA. Using 1 kΩ for R1 limits the worst-case short-circuit current to 3.3 mA (3.3V / 1000Ω), protecting the silicon. The 1 µF capacitance is a standard, low-cost value that avoids the parasitic inductance found in larger electrolytic cans. The math checks out via the standard RC formula: f_c = 1 / (2πRC). For 1 kΩ and 1 µF, f_c = 159.15 Hz per stage.
Why This Topology Over the Alternatives?
When designing a capacitor circuit diagram for PWM smoothing, you generally have three choices. Here is how the cascaded passive RC stack compares to the alternatives.
| Criteria | 1st-Order Passive RC | 2nd-Order Cascaded RC (Our Choice) | Active Sallen-Key (Op-Amp) |
|---|---|---|---|
| Roll-off Rate | -20 dB/decade | -40 dB/decade | -40 dB/decade (or higher) |
| Ripple Attenuation (at 5kHz) | ~ -30 dB | ~ -60 dB (theoretical) | ~ -60 dB+ |
| Component Count | 2 (1R, 1C) | 4 (2R, 2C) | 6+ (2R, 2C, Op-Amp, decoupling) |
| Power Requirement | None | None | Requires dual or single supply rail |
| Output Impedance | Low (R value) | Medium (R1 + R2 = 2 kΩ) | Near Zero (Op-Amp driven) |
We choose the 2nd-order cascaded RC because it hits the sweet spot for hobbyist and prototyping environments. It provides aggressive ripple attenuation without requiring a separate op-amp IC, dual power rails, or complex compensation networks. The 2 kΩ total output impedance is easily buffered by the high-impedance input of an ADC (like the ADS1115) or a unity-gain op-amp if you need to drive a heavier load.
Element Behavior Matrix and Extreme Failure Modes
Understanding how a capacitor circuit diagram behaves when components drift or fail is critical for debugging. Below is the behavior matrix for component changes, followed by hard failure modes.
Component Drift Behavior
| Change | Effect on Cutoff Frequency | Effect on Step Settling Time | Effect on Output Impedance |
|---|---|---|---|
| Increase R1 or R2 | Decreases (filter becomes slower) | Increases (takes longer to reach final DC value) | Increases (worse for driving loads) |
| Increase C1 or C2 | Decreases (better ripple rejection) | Increases (sluggish response to PWM duty changes) | No direct change |
| Decrease C1 or C2 | Increases (more ripple passes through) | Decreases (faster response) | No direct change |
Extreme Failure Modes (Shorts and Opens)
- C1 Shorts to GND: Node_A is pulled to 0V. Vout drops to 0V. The microcontroller GPIO will source current through R1. Because R1 is 1 kΩ, current is limited to 3.3 mA, so the GPIO survives, but the circuit ceases to function.
- C2 Shorts to GND: Vout is pulled directly to 0V. Node_A continues to filter, but the final output is dead. Similar to C1, R1+R2 limit the short-circuit current to 1.65 mA.
- R1 Opens: The signal path is broken. Node_A and Node_B float. Vout will read random noise or drift to 0V due to capacitor leakage. The multimeter will read infinite resistance across R1.
- R2 Opens: Node_A functions as a 1st-order filter, but Node_B is disconnected from the signal path. Vout floats. An ADC connected to Vout will read erratic, floating values.
Step-by-Step Breadboard Testing and Verification
Follow this exact sequence to build and verify the circuit on a solderless breadboard. This assumes you are using an ESP32 and a basic digital storage oscilloscope (DSO).
- De-energize and Prep: Unplug the ESP32 USB cable. Ensure the 3.3V and GND rails on your breadboard are clear.
- Place R1: Insert a 1 kΩ resistor bridging the center trench. Connect one leg to the ESP32 GPIO 25 (via jumper wire) and the other leg to an empty node (Node_A).
- Place C1: Insert the 1 µF ceramic capacitor at Node_A, with the other leg tied directly to the GND rail.
- Place R2: Insert the second 1 kΩ resistor with one leg at Node_A and the other leg at a new empty node (Node_B).
- Place C2: Insert the second 1 µF capacitor at Node_B, with the other leg tied to the GND rail.
- Continuity Check: Before applying power, use your multimeter in continuity mode. Probe Vout (Node_B) to GND. You should see a brief spike (capacitors charging the meter's internal battery) followed by an open circuit (OL). If it reads a dead short (0.0 Ω), you have a breadboard short or a blown capacitor. Fix it before proceeding.
- Power and Code: Plug in the ESP32. Flash a simple Arduino sketch using
ledcSetup(0, 5000, 8);andledcWrite(0, 128);to output a 50% duty cycle 5kHz PWM signal. - Scope Verification: Connect your oscilloscope probe to Vout. Set the timebase to 2ms/div and voltage to 1V/div. You should see a flat, steady line at ~1.65V (half of 3.3V). If you see a sawtooth ripple exceeding 20mV peak-to-peak, check your capacitor dielectric type or verify your PWM frequency isn't accidentally set to 50Hz.
Frequently Asked Questions
How do I read a polarized capacitor circuit diagram for this filter?
In a standard capacitor circuit diagram, a polarized capacitor (like an electrolytic or tantalum) is denoted by one straight plate (positive/anode) and one curved plate (negative/cathode), often accompanied by a '+' sign. For our PWM filter, we strongly recommend non-polarized ceramic capacitors (denoted by two parallel straight lines). If you must use electrolytics due to needing massive capacitance (e.g., 100 µF for a 1Hz cutoff), ensure the anode connects to the signal side (Node_A/Node_B) and the cathode connects to GND. Wiring them backward will cause the dielectric oxide layer to break down, leading to high leakage current, overheating, and potentially a venting failure.
What breaks if I use an electrolytic instead of ceramic in this capacitor circuit diagram?
Electrolytic capacitors have high Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL). At a 5kHz PWM switching frequency, the ESL of a standard aluminum electrolytic capacitor begins to dominate its impedance, effectively turning it into an inductor rather than a capacitor. This means high-frequency ripple will pass straight through to Vout. Furthermore, electrolytics have wide tolerance bands (often -20% / +80%), meaning your 159 Hz cutoff could easily drift to 120 Hz or 250 Hz. Stick to multilayer ceramic capacitors (MLCCs) for anything above 100 Hz.
Can I scale this capacitor circuit diagram for high-current audio applications?
No, not directly. This specific passive RC topology relies on the resistors to drop voltage and isolate the stages. If you attempt to drive an 8Ω speaker or a low-impedance audio amplifier input directly from Vout, the load impedance will parallel with C2, completely destroying the filter's cutoff frequency and causing massive signal attenuation. For audio applications (where you need to pass 20Hz-20kHz but block high-frequency DAC switching noise), you must buffer the Vout node with a unity-gain operational amplifier (like the OPA2134 or TL072) to provide the necessary low output impedance and current drive capability. For deeper reading on active filter scaling, refer to the Texas Instruments filter design guide.
