SPI (Serial Peripheral Interface) bus communication is a synchronous, full-duplex, four-wire protocol used to move data quickly between a microcontroller and peripheral ICs over short distances. Unlike I2C, SPI pushes data in both directions simultaneously and relies on individual Chip Select (CS) lines rather than software addressing. This makes it the undisputed choice for high-speed SD cards, TFT displays, and external flash memory on the bench. If you need to move megabytes of data rather than a few sensor bytes, SPI is your protocol.
The Physical Layer: Wiring and Bus Mechanics
You cannot debug a protocol you do not understand at the physical layer. SPI operates on a master-slave (or controller-peripheral) architecture using four shared logic lines. Before writing a single line of code, you must understand the bus mechanics and the physical pull-up requirements that separate a stable circuit from a flaky one.
| Parameter | SPI Specification | Practical Maker Reality |
|---|---|---|
| Wires | 4 shared (SCK, MOSI, MISO, CS) | CS is individual per device; the other three are shared across the bus. |
| Speed | 10 MHz to 80+ MHz | ESP32 can push 80 MHz, but long breadboard wires will cause signal reflection above 10 MHz. |
| Addressing | None (Hardware CS lines) | Every slave needs its own GPIO for Chip Select. Pin count limits device count. |
| Distance | Short (Typically < 1 meter) | High clock speeds degrade over distance. Keep traces tight; avoid ribbon cables for SCK. |
The Pull-Up Rule: Why Your CS Line Needs a Resistor
A common misconception is that SPI requires pull-up resistors on the data lines like I2C does. It does not. MOSI, MISO, and SCK are actively driven push-pull lines. However, the Chip Select (CS) line must have a 10kΩ pull-up resistor to VCC. When your microcontroller boots, its GPIO pins are temporarily high-impedance (floating). Without a pull-up, the floating CS line can glitch low, causing the slave IC to interpret boot noise as a command and lock up before your code even starts. Always solder a 10kΩ resistor between CS and 3.3V.
Protocol Selection: When to Use SPI vs I2C vs UART
Choosing the right protocol depends entirely on your constraints regarding distance, speed, and device count. Here is the decision framework for your next PCB or breadboard layout.
| Criteria | SPI | I2C | UART |
|---|---|---|---|
| Best For | High-speed data (Displays, Flash, ADC) | Low-speed sensor polling, pin-constrained MCUs | Point-to-point debug, GPS, cellular modems |
| Max Speed | ~80 MHz (MCU dependent) | ~3.4 MHz (Fast-mode Plus) | ~3 Mbps (Typical UART limit) |
| Bus Topology | Multi-slave, single master (usually) | Multi-master, multi-slave | Point-to-point only |
| Device Count Limit | Limited by available MCU GPIOs for CS | Limited by 7-bit/10-bit address space (up to 128) | 1 to 1 (without multiplexers) |
Choose SPI when: You are driving a TFT screen, reading an SD card, or need to sample an ADC at high rates.
Choose I2C when: You are connecting five different environmental sensors and only have two GPIO pins available.
Choose UART when: You are talking to a PC serial monitor, a GPS module, or an ESP8266 AT-command firmware.
Minimal Working Exchange: ESP32 to SPI Flash
Let us build a minimal, working exchange. We will wire an ESP32 DevKit V1 to a W25Q32 SPI Flash chip and read its JEDEC Manufacturer ID. This proves the physical layer and timing are correct before you attempt complex file system operations.
Physical Wiring Table
| W25Q32 Flash Pin | ESP32 DevKit V1 GPIO | Notes |
|---|---|---|
| VCC | 3V3 | Do not use 5V; W25Q32 is a 3.3V part. |
| GND | GND | Common ground is mandatory. |
| CS (Chip Select) | GPIO 5 | Add 10kΩ pull-up to 3V3! |
| CLK (Clock) | GPIO 18 (SCK) | Default VSPI clock pin. |
| DI (MOSI) | GPIO 23 (MOSI) | Master Out, Slave In. |
| DO (MISO) | GPIO 19 (MISO) | Master In, Slave Out. |
Arduino Code: Reading the JEDEC ID
This code uses the hardware VSPI bus. We explicitly define the SPI settings to ensure the clock polarity and phase match the W25Q32 datasheet requirements (Mode 0).
#include
// Define the Chip Select pin
#define CS_PIN 5
// The W25Q32 supports up to 104MHz, but we use 10MHz for breadboard stability
SPISettings spiSettings(10000000, MSBFIRST, SPI_MODE0);
void setup() {
Serial.begin(115200);
pinMode(CS_PIN, OUTPUT);
digitalWrite(CS_PIN, HIGH); // Deselect slave immediately
SPI.begin(); // Initialize default VSPI bus
Serial.println("SPI Bus Initialized. Reading JEDEC ID...");
}
void loop() {
uint8_t manufacturer, memType, capacity;
// Begin transaction with specific clock and mode settings
SPI.beginTransaction(spiSettings);
digitalWrite(CS_PIN, LOW); // Assert Chip Select
// Send JEDEC ID command (0x9F)
SPI.transfer(0x9F);
// Read the 3 response bytes
manufacturer = SPI.transfer(0x00);
memType = SPI.transfer(0x00);
capacity = SPI.transfer(0x00);
digitalWrite(CS_PIN, HIGH); // Deassert Chip Select
SPI.endTransaction();
Serial.printf("Manufacturer: 0x%02X, Type: 0x%02X, Capacity: 0x%02X\n",
manufacturer, memType, capacity);
// Winbond should return 0xEF, 0x40, 0x16 for W25Q32
delay(2000);
} Debugging the Bus: Sniffing and Classic Failures
When your SPI device returns garbage data, do not guess. Hook up a logic analyzer. A $15 FX2LP clone running sigrok PulseView or a Saleae Logic Pro 8 will show you exactly where the physical layer is failing.
The Classic Failures
- Baud Mismatch and CPOL/CPHA Errors: The most common SPI failure is a clock polarity/phase mismatch. SPI defines four modes (0 to 3) based on whether the clock idles high or low (CPOL) and whether data is sampled on the leading or trailing edge (CPHA). If your master is in Mode 0 but the slave expects Mode 3, the data will be shifted by one bit, resulting in total corruption. Always check the slave datasheet's timing diagram.
- Missing CS Pull-Up: If your circuit works fine until you press the MCU reset button, and then the slave stops responding, you have a floating CS line glitch. Add the 10kΩ pull-up resistor.
- 'Address Clash' (CS Contention): Unlike I2C, SPI does not use software addresses, so you cannot have an 'address clash' in the traditional sense. The SPI equivalent is CS line contention. This happens when you wire two slaves to the same CS pin because you ran out of GPIOs, or when a GPIO expander fails to isolate the lines. When two slaves are asserted simultaneously, their MISO outputs fight each other, potentially shorting VCC to GND and frying the output buffers.
- Setup and Hold Time Violations: At speeds above 20 MHz, the physical length of your wires matters. If the SCK signal arrives at the slave slightly after the MOSI data changes (due to capacitive loading on long breadboard wires), the slave will sample the wrong bit. Lower the baud rate or shorten the wires.
Frequently Asked Questions
Can SPI bus communication work over long distances?
Standard SPI is designed for on-board communication, typically under 30 cm. Pushing SPI over 1 meter at high speeds results in severe signal degradation due to capacitance and crosstalk. If you must run SPI over long distances, you need to use differential line drivers (like RS-422 transceivers) to convert the single-ended logic signals into differential pairs, or drastically reduce the clock speed to under 1 MHz.
How do I connect multiple SPI devices to one ESP32?
You share the SCK, MOSI, and MISO lines across all devices, but every single device must have its own dedicated Chip Select (CS) wire connected to a unique GPIO on the ESP32. If you run out of GPIOs, use a 74HC138 3-to-8 line decoder to expand a single CS line into eight, or use an I2C GPIO expander like the MCP23017 to manage the CS pins.
Why is my SPI device returning all 0xFF or 0x00?
If your logic analyzer shows the master sending data but the MISO line is stuck high (0xFF) or low (0x00), the slave is not responding. This almost always means the CS line is not being pulled low, the slave is unpowered, or you have MISO and MOSI swapped. Remember: Master MOSI connects to Slave MOSI (or DI), and Master MISO connects to Slave MISO (or DO).
What is the difference between SPI Mode 0 and Mode 3?
Mode 0 and Mode 3 both sample data on the leading edge of the clock pulse, but they differ in the idle state of the clock. In Mode 0, the clock idles LOW (CPOL=0). In Mode 3, the clock idles HIGH (CPOL=1). According to Espressif ESP-IDF documentation, most modern sensors and flash chips default to Mode 0, but always verify the timing diagram in your specific component's datasheet.
