An I2C timing diagram maps the exact microsecond-level relationship between the Serial Clock (SCL) and Serial Data (SDA) lines. Rather than just showing logical ones and zeros, the diagram reveals the physical constraints of the bus: setup times, hold times, Start/Stop conditions, and clock stretching. If your ESP32 is throwing I2C timeout errors or your Arduino is failing to read a BME280 sensor, the answer is almost always hiding in the physical layer timing.
The I2C Physical Layer and Bus Mechanics
Before reading the timing diagram, you must understand the physical wiring. I2C uses an open-drain (or open-collector) architecture. This means devices can only pull the SDA and SCL lines LOW (to ground); they cannot drive them HIGH. To achieve a HIGH state, the bus relies on external pull-up resistors connected to VCC (typically 3.3V or 5V).
For a standard 100kHz bus with a few devices, use 4.7kΩ pull-ups. If you push to Fast Mode (400kHz), the parasitic capacitance of the wires requires stronger pull-ups—drop to 2.2kΩ. For Fast+ (1MHz), use 1kΩ. Never connect I2C lines directly to VCC without resistors; you will short the bus when a device pulls the line low.
| Feature | Specification Details |
|---|---|
| Wires Required | 2 shared lines (SDA, SCL) + common Ground |
| Speed Modes | Standard (100kHz), Fast (400kHz), Fast+ (1MHz), High-speed (3.4MHz) |
| Addressing | 7-bit (128 addresses, ~16 reserved) or 10-bit (1024 addresses) |
| Max Distance | ~1 meter at 100kHz; ~30cm at 1MHz (without active bus buffers like the PCA9600) |
| Topology | Multi-master, multi-slave shared bus |
The timing diagram enforces strict boundaries on how fast these lines can transition. The NXP I2C-bus specification (UM10204) defines these limits to ensure data is sampled correctly despite varying parasitic capacitance across different PCB layouts.
| Parameter | Symbol | Standard (100kHz) | Fast (400kHz) | Fast+ (1MHz) | Unit |
|---|---|---|---|---|---|
| SCL Clock Frequency | fSCL | 0 - 100 | 0 - 400 | 0 - 1000 | kHz |
| SDA Setup Time | tSU;DAT | 250 | 100 | 50 | ns |
| SDA Hold Time | tHD;DAT | 300 | 300 | 0 | ns |
| START Condition Setup | tSU;STA | 4.7 | 0.6 | 0.26 | µs |
| STOP Condition Setup | tSU;STO | 4.0 | 0.6 | 0.26 | µs |
Decoding the I2C Timing Diagram: Start, Stop, and Data Bits
A timing diagram visualizes voltage over time. The top trace is SCL, the bottom is SDA. Here is how to read the core mechanics of a minimal working exchange.
1. The START and STOP Conditions
Because I2C has no dedicated chip-select line like SPI, it needs a way to wake up the bus.
- START Condition: SDA transitions from HIGH to LOW while SCL is HIGH. This is the only time SDA is allowed to change while the clock is high.
- STOP Condition: SDA transitions from LOW to HIGH while SCL is HIGH.
2. Data Bits and the ACK/NACK
After the START condition, the master clocks out 8 bits (usually a 7-bit address + 1 Read/Write bit). The timing diagram shows SDA stabilizing during the SCL LOW phase (Setup Time) and remaining rigid while SCL pulses HIGH (Hold Time). The receiver samples SDA on the rising edge of SCL.
The 9th Clock Pulse (ACK/NACK): After 8 bits, the master releases the SDA line (letting the pull-up resistor take it HIGH) but continues to pulse SCL. If the slave successfully received the byte, it pulls SDA LOW during this 9th pulse (ACK). If SDA stays HIGH, it's a NACK, meaning the slave is missing, busy, or didn't recognize the address.
3. Clock Stretching
Clock stretching is a hardware flow-control mechanism. If a slave (like a booting microcontroller or a slow ADC) needs more time to process data, it physically holds the SCL line LOW after the master releases it. The master's timing diagram will show the SCL HIGH period extending unpredictably until the slave releases the line. The Espressif ESP-IDF I2C driver documentation explicitly warns about this: the ESP32 hardware I2C peripheral has a hardcoded timeout for clock stretching (often ~13ms). If a slave stretches the clock longer than this threshold, the ESP32 will abort the transaction and throw an I2C timeout error.
Classic I2C Failures and How to Sniff the Bus
When your code fails, don't just rewrite the library. Hook up an oscilloscope or a logic analyzer (like the Saleae Logic Pro 8) and look at the physical waveforms. Here are the three most common hardware failures.
Missing or Undersized Pull-Up Resistors
The Symptom: The Saleae I2C protocol analyzer shows valid packets, but your oscilloscope reveals 'shark fin' waveforms. The falling edges are sharp (transistor pulling to ground), but the rising edges are slow, exponential curves.
The Cause: Parasitic capacitance on the SDA/SCL lines combined with weak (or missing) pull-up resistors forms a low-pass RC filter. The voltage never reaches the logic HIGH threshold before the next clock pulse.
The Fix: Add 4.7kΩ pull-ups to VCC. If running at 400kHz, drop to 2.2kΩ.
Address Clashes
The Symptom: The bus locks up, or data reads as corrupted garbage.
The Cause: Two devices share the same 7-bit address. A classic example is using two cheap PCF8574-based 1602 LCD backpacks, both hardcoded to 0x27.
The Fix: Check the datasheet. Bridge the A0, A1, or A2 solder pads on the back of one module to shift its address (e.g., to 0x26 or 0x25).
Baud Mismatch and Bus Lockups
The Symptom: The master sends a START, but the SDA line gets stuck LOW indefinitely.
The Cause: A master reset mid-transaction while the slave was outputting a LOW data bit. The slave is still holding SDA low, waiting for clock pulses that the newly rebooted master isn't sending.
The Fix: Implement a bus recovery routine. On boot, configure the SCL pin as a standard GPIO output and manually toggle it HIGH and LOW 9 times. This forces the stuck slave to clock out its remaining bits and release the SDA line, after which you can re-initialize the I2C peripheral.
I2C vs. SPI vs. UART: Protocol Selection Matrix
I2C is not the right tool for every job. Use this matrix to decide which protocol fits your specific distance, speed, and device count requirements.
| Criteria | I2C | SPI | UART |
|---|---|---|---|
| Wires Required | 2 (SDA, SCL) | 4 (MOSI, MISO, SCK, CS) | 2 (TX, RX) |
| Max Speed (Typical) | 400 kHz (Fast) / 1 MHz (Fast+) | 10 MHz to 50+ MHz | 115,200 baud (standard) / 3 Mbps |
| Topology / Device Count | Bus (up to 112 standard devices) | Point-to-Multipoint (1 CS wire per device) | Point-to-Point (1 TX/RX pair) |
| Max Distance (Unbuffered) | ~1 meter | ~30 cm (highly signal-dependent) | ~15 meters (at 9600 baud) |
| Hardware Complexity | Low (built-in address routing) | Medium (requires CS management) | Low (simple FIFO buffers) |
- Choose I2C when: You have multiple low-speed sensors (temperature, humidity, IMUs) on the same PCB and want to minimize pin count and trace routing.
- Choose SPI when: You need high throughput (SD cards, TFT displays, external flash) and have enough GPIO pins to dedicate to individual Chip Select lines.
- Choose UART when: You are communicating over longer distances (RS-485 transceivers), talking to a PC via USB-to-Serial, or connecting standalone modules like GPS receivers or cellular modems.
Mastering the I2C timing diagram bridges the gap between writing code that 'should' work and building hardware that actually does. Always verify your pull-up sizing, respect the setup and hold times in your PCB layout, and keep a logic analyzer on your bench for when the bus inevitably locks up.
