The Physical Layer: Wiring, Pull-Ups, and Bus Mechanics
Before analyzing an I2C bus timing diagram on a logic analyzer, you must understand the physical layer that generates those waveforms. Unlike push-pull protocols like SPI, I2C uses open-drain (or open-collector) outputs. This means devices can only pull the bus lines LOW; they cannot drive them HIGH. To return the lines to a HIGH state, external pull-up resistors are strictly required.
If you wire an I2C bus without pull-ups, the SDA and SCL lines will float, resulting in undefined logic levels and a completely corrupted timing diagram. The NXP I2C-bus specification (UM10204) dictates strict limits on bus capacitance and rise times, which directly govern your resistor selection.
I2C Bus Mechanics Specification
| Feature | Standard Mode | Fast Mode | Fast Mode Plus |
|---|---|---|---|
| Wires Required | 2 (SDA, SCL) + GND | 2 (SDA, SCL) + GND | 2 (SDA, SCL) + GND |
| Clock Speed (SCL) | 100 kHz | 400 kHz | 1 MHz |
| Addressing | 7-bit or 10-bit | 7-bit or 10-bit | 7-bit or 10-bit |
| Max Bus Capacitance | 400 pF | 400 pF | 550 pF |
| Typical Max Distance | ~1 meter | ~30 cm | ~10 cm |
| Standard Pull-Up | 4.7 kΩ | 2.2 kΩ | 1.0 kΩ |
The rise time ($t_r$) of the I2C bus is governed by the RC time constant: $t_r \approx 0.8473 \times R_p \times C_b$. For Fast Mode (400 kHz), the max rise time is 300 ns. If your bus capacitance ($C_b$) is 200 pF, your maximum pull-up resistor ($R_p$) is $300ns / (0.8473 \times 200pF) \approx 1.77 k\Omega$. Using a standard 4.7 kΩ resistor here will cause the timing diagram to show rounded, failing waveforms.
Reading an I2C Bus Timing Diagram: Start, Stop, and Data
When you hook up a logic analyzer (like a Saleae Logic Pro 8 or DSLogic Plus) and decode the SDA and SCL lines, the I2C bus timing diagram reveals the exact sequence of the transaction. Because the bus is idle-HIGH, all transactions begin and end with specific SDA transitions while the clock is active.
The Minimal Working Exchange
A standard single-byte write to a sensor (like a BMP280) follows this exact sequence on the timing diagram:
- START Condition (S): The master pulls SDA LOW while SCL remains HIGH. This is the only time SDA is allowed to change state while SCL is HIGH.
- Slave Address (7 bits): The master clocks out the 7-bit target address (e.g.,
0x76for BMP280) on the SDA line, sampled on the rising edge of SCL. - R/W Bit (1 bit): A LOW bit indicates a Write; a HIGH bit indicates a Read.
- ACKnowledge (ACK): The master releases SDA (pulls HIGH via resistor). The target slave pulls SDA LOW during the 9th SCL clock pulse to acknowledge receipt.
- Data Byte (8 bits): The master clocks out the register address or data payload.
- ACKnowledge (ACK): The slave pulls SDA LOW again to confirm the data byte.
- STOP Condition (P): The master releases SDA to go HIGH while SCL is HIGH, returning the bus to the idle state.
Data validity is strict: the SDA line must remain completely stable during the HIGH period of the SCL pulse. SDA is only permitted to transition when SCL is LOW.
Debugging the Classics: Sniffing the Bus and Fixing Failures
When your microcontroller throws an I2C timeout or returns 0xFF for every register read, the physical timing diagram holds the answer. Here is how to diagnose the three most common I2C failures using a logic analyzer or oscilloscope.
1. Missing or Undersized Pull-Ups (The Rounded Waveform)
Symptom: The logic analyzer shows SDA and SCL dropping sharply to 0V, but the rise back to 3.3V looks like a slow, rounded exponential curve rather than a square wave. The bus fails to reach the logic HIGH threshold ($V_{IH}$) before the next clock edge.
Fix: Decrease your pull-up resistor value. If you are using 10 kΩ on a Fast Mode bus with multiple sensors, drop to 2.2 kΩ. If the bus is heavily loaded (near the 400 pF limit), you may need an active pull-up circuit or a dedicated I2C bus buffer like the PCA9600.
2. Address Clashes and NACKs
Symptom: The timing diagram shows a valid START and Address byte, but on the 9th clock pulse (the ACK bit), SDA stays HIGH. This is a Not-Acknowledge (NACK).
Fix: A NACK on the address byte means no device recognized the address. Verify your wiring, ensure the device has power, and check for address clashes. Many breakout boards have a physical solder jumper to shift the I2C address (e.g., shifting an MPU6050 from 0x68 to 0x69). Use an I2C scanner script to map the live bus.
3. Clock Stretching Timeouts
Symptom: The master drives SCL LOW, but it stays LOW for an abnormally long time (milliseconds instead of microseconds) before the next rising edge.
Fix: This is clock stretching. A slave device is holding SCL LOW because it needs more time to process data (common in ADCs or complex sensors). If your master (like a Raspberry Pi) has a hardware timeout limit, it will abort the transaction. Ensure your master's I2C driver supports clock stretching, or increase the bus timeout threshold in your OS/device tree settings.
Protocol Selection: When to Choose I2C Over SPI or UART
I2C is not the universal answer for embedded communication. Use this matrix to decide which protocol fits your distance, speed, and device count requirements.
| Criteria | I2C | SPI | UART |
|---|---|---|---|
| Wiring Complexity | 2 shared wires (SDA, SCL) | 4 wires (MOSI, MISO, SCK, CS) + extra CS per device | 2 wires (TX, RX) per pair |
| Max Speed | 1 Mbps (Fast Mode Plus) | 10+ MHz (Limited by trace capacitance) | Typically 115.2 kbps to 3 Mbps |
| Device Count | Up to 127 (7-bit) on 2 wires | Requires individual Chip Select (CS) wire for each | Point-to-point (1 master, 1 slave) |
| Best Use Case | Low-speed sensors, EEPROMs, OLEDs on the same PCB | High-speed data (SD cards, TFT displays, external flash) | Off-board communication, GPS modules, PC serial consoles |
Choose I2C when you need to connect multiple low-to-medium speed sensors without exhausting your microcontroller's GPIO pins on individual chip select lines. Choose SPI when bandwidth is critical, and UART when communicating over longer distances or with legacy PC equipment.
I2C Timing and Troubleshooting FAQ
How do I calculate the correct I2C pull-up resistor value?
You must calculate both the minimum and maximum bounds. The minimum resistance is dictated by the maximum sink current ($I_{OL}$) of your devices, typically 3 mA. For a 3.3V bus, $R_{min} = (3.3V - 0.4V) / 3mA = 966 \Omega$. The maximum resistance is dictated by the bus capacitance ($C_b$) and the required rise time ($t_r$). Use the formula $R_{max} = t_r / (0.8473 \times C_b)$. Always pick a standard resistor value (like 2.2 kΩ or 4.7 kΩ) that falls safely between these two bounds.
Why does my I2C bus timing diagram show rounded square waves instead of sharp edges?
Rounded edges indicate that the RC time constant of the bus is too high. This is caused by either excessive parasitic capacitance (long wires, too many breakout boards, or unshielded ribbon cables) or a pull-up resistor value that is too large. To fix this, shorten your wire runs, reduce the pull-up resistor value (e.g., from 4.7 kΩ down to 1 kΩ), or lower the I2C clock speed to Standard Mode (100 kHz) to give the bus more time to reach the logic HIGH threshold.
What is clock stretching and how does it affect the timing diagram?
Clock stretching is a flow-control mechanism where a slave device holds the SCL line LOW after receiving a byte, delaying the master's next clock pulse until the slave is ready to proceed. On a timing diagram, this appears as an abnormally wide LOW pulse on the SCL line. While perfectly valid in the I2C specification, some hardware I2C controllers (particularly on older Raspberry Pi SoCs) do not support clock stretching natively and will flag a timeout error. In those cases, you must use software I2C (bit-banging) or select a sensor that does not stretch the clock.
Can I mix 3.3V and 5V devices on the same I2C bus?
Not directly without risking damage to the 3.3V device. If you pull the bus up to 5V, the 3.3V microcontroller's GPIO pins will be subjected to overvoltage when the bus is idle. To safely mix voltages, use a bidirectional logic level shifter (like the BSS138 MOSFET-based shifter or a dedicated IC like the PCA9306). The shifter isolates the two voltage domains, allowing the 5V side to pull up to 5V and the 3.3V side to pull up to 3.3V while safely translating the open-drain signals.
For deeper electrical specifications and timing thresholds, always consult the Analog Devices I2C Primer and your specific microcontroller's datasheet, as local board trace capacitance can heavily influence real-world bus behavior.
