A combination type arc fault circuit interrupter (AFCI) is a specialized protective device that detects both series arcs (loose connections in a single wire) and parallel arcs (current jumping across insulation between conductors). Unlike older branch-only AFCIs, combination types analyze high-frequency current noise superimposed on the 60Hz fundamental to identify the chaotic, broad-spectrum RF signature of an electrical arc. While UL-listed mains breakers are proprietary and sealed, understanding the DSP and analog front-end (AFE) topology is essential for embedded engineers designing smart panels, arc signature analyzers, or predictive maintenance IoT nodes.
In this guide, we will design a low-voltage, breadboard-safe analog sensing topology that feeds an ESP32-S3 microcontroller. This circuit isolates the high-frequency arc envelope, allowing the microcontroller to sample and classify arc events without requiring a multi-megasample-per-second ADC.
The Sensing Topology: Nodes and Component Values
To detect arcs, we must extract high-frequency noise (typically 10kHz to 100MHz) while rejecting the massive 60Hz fundamental current. We achieve this using a Current Transformer (CT), a high-pass filter, and a precision envelope detector. Here is the design walkthrough with exact component values for a 12V AC breadboard prototype.
- $N_{CT}$ (Current Transformer Node): We use a Talema AS-100 (1000:1 turns ratio). The primary is the AC load wire. The secondary connects to a 100Ω burden resistor (1% tolerance, 1W) to convert the induced current into a measurable voltage. At 10A primary, this yields 10mA secondary, or 1V RMS across the burden.
- $N_{HPF}$ (High-Pass Filter Node): A first-order CR high-pass filter blocks the 60Hz fundamental. We use a 100nF film capacitor in series with a 1kΩ resistor to ground. This sets the cutoff frequency at roughly 1.5kHz, heavily attenuating the 60Hz wave while passing arc-induced high-frequency transients.
- $N_{RECT}$ (Precision Rectifier Node): Standard diodes have a 0.3V forward drop that blinds the MCU to micro-arcs. We use an OPA350 op-amp configured as a precision rectifier with BAT54S Schottky diodes in the feedback loop. The OPA350's high slew rate (9V/µs) ensures it can track the fast HF transients without phase inversion.
- $N_{ENV}$ (Envelope / ADC Input Node): The rectified signal feeds an RC peak-hold network consisting of a 10nF hold capacitor and a 10kΩ bleeder resistor. This creates a DC envelope representing the arc's high-frequency energy. This node connects directly to GPIO4 (ADC1_CH3) on the ESP32-S3-WROOM-1.
Why This Envelope Topology Over Direct RF Sampling?
When designing the AFE for a combination type arc fault circuit interrupter, engineers face a choice: use a high-speed ADC to sample the raw RF waveform directly, or use an analog envelope detector to extract the energy profile. We chose the analog envelope topology for embedded prototyping for three critical reasons:
- ADC Bandwidth Limitations: Direct RF sampling requires an ADC running at >2MSPS to satisfy the Nyquist theorem for 100MHz arc noise. The ESP32-S3's internal SAR ADC maxes out around 83kSPS in continuous mode, which is entirely insufficient for raw RF capture.
- Processing Overhead: Running a real-time Fast Fourier Transform (FFT) on 2MSPS data requires a dedicated DSP or FPGA. By using an analog envelope detector, we compress the high-frequency burst into a low-frequency DC envelope (0-5kHz bandwidth). The ESP32-S3 can easily sample this at 10kSPS and run a simple threshold-and-duration algorithm.
- Cost and Board Space: A 16-bit, 2MSPS SPI ADC (like the AD7928) costs roughly $8-$12 and requires strict PCB layout rules to avoid digital noise coupling. The OPA350 and passive envelope network cost under $2 and are highly forgiving on a solderless breadboard.
Behavior Matrix: Element Changes and Failure Extremes
Understanding how the analog front-end reacts to component drift or catastrophic failure is vital for debugging. The table below contrasts nominal behavior with the extremes of short and open circuits.
| Component / Node | Nominal Change Effect | Short Circuit Extreme | Open Circuit Extreme |
|---|---|---|---|
| Burden Resistor (100Ω) | Higher value increases ADC resolution but risks CT core saturation. | CT secondary shorted. Safe for CT, but $N_{HPF}$ sees 0V. No arc detection. | CT secondary open. Dangerous: Generates lethal high-voltage spikes that will destroy the op-amp and risk shock. |
| HPF Capacitor (100nF) | Lower value raises cutoff frequency, potentially filtering out low-frequency parallel arcs. | Passes 60Hz fundamental directly to op-amp. Op-amp rails out, blinding the ADC to HF noise. | Blocks all current. $N_{RECT}$ floats to 0V. System reads zero arc energy constantly. |
| Hold Capacitor (10nF) | Higher value smooths the envelope but increases response lag (misses short micro-arcs). | Pulls $N_{ENV}$ to ground. ADC reads 0V regardless of arc presence. | Envelope does not hold. ADC reads raw, jagged rectified HF noise, causing false software trips. |
| Feedback Diode (BAT54S) | Using standard 1N4148 introduces 0.6V dead-zone, missing low-energy series arcs. | Op-amp output shorts to inverting input. Output locks at 0V. No rectification. | Op-amp operates open-loop. Output saturates to positive rail (3.3V) on any transient noise. |
Step-by-Step Breadboard Verification
Testing arc fault circuits on 120V/240V mains is extremely dangerous and violates safe bench practices. We will breadboard and verify this topology using a safe 12V AC isolated source and a mechanical carbon-arc generator.
- Prepare the Isolated AC Source: Connect a 120V-to-12V step-down transformer (e.g., a 12V 2A wall wart with AC output, or a dedicated bench transformer) to your breadboard's power rails. Verify with a multimeter that the output is strictly 12V AC and isolated from earth ground.
- Wire the CT and Burden: Pass one of the 12V AC secondary wires through the center of the Talema AS-100. Connect the CT's secondary leads across the 100Ω burden resistor. Connect an oscilloscope probe across the burden resistor. You should see a clean 12V AC sine wave scaled down to roughly 1.2V RMS (assuming a 10A load, or proportionally less for smaller loads).
- Build and Probe the HPF: Insert the 100nF capacitor and 1kΩ resistor. Probe $N_{HPF}$. The 60Hz waveform should be attenuated by at least -20dB, leaving only a tiny ripple. If you see a full sine wave, your capacitor is likely shorted or the wrong value.
- Verify the Precision Rectifier: Power the OPA350 with 3.3V and GND. Probe $N_{RECT}$. When you snap a mechanical switch in the load path to create a micro-arc, you should see sharp, positive-going DC pulses corresponding to the high-frequency noise bursts.
- Test the Envelope and ESP32 ADC: Connect $N_{ENV}$ to GPIO4. Flash the ESP32-S3 with a simple continuous ADC sampling script using the ESP-IDF ADC oneshot driver. Open the serial plotter. When you create a deliberate loose connection (scraping a wire against a carbon rod or a loose terminal), the plotted envelope should spike sharply above the 50mV noise floor and decay over 10-20ms.
FAQ: Combination Type Arc Fault Circuit Interrupter Engineering
What makes a combination type arc fault circuit interrupter different from branch/feeder types?
Older 'branch/feeder' AFCIs were designed primarily to detect parallel arcs (high-current short circuits across damaged insulation) and typically required 75A of peak current to trigger. They were largely blind to series arcs. A combination type arc fault circuit interrupter, mandated by the NFPA 70 (NEC) for most residential living spaces, uses advanced DSP to detect the lower-energy, high-frequency signatures of series arcs (like a loose screw on a receptacle) down to 5A. The 'combination' refers to its ability to protect against both series and parallel arc faults in the branch circuit and the downstream cords.
How does a combination type arc fault circuit interrupter ignore normal brushed motor noise?
Brushed motors (in vacuums or drills) generate high-frequency commutator noise that looks remarkably similar to an arc. To prevent nuisance tripping, the MCU algorithm analyzes the timing of the noise relative to the 60Hz zero-crossing. Arcs are chaotic and occur randomly across the AC waveform. Brushed motor noise, however, is highly synchronous and often masks out or spikes at specific, predictable phase angles. Furthermore, algorithms look for 'shoulders' or gaps in the current waveform near the zero-crossing—a hallmark of the ionization/de-ionization cycle of a true air-gap arc, which arc fault analysis literature identifies as a primary distinguishing feature.
Why does my combination type arc fault circuit interrupter prototype trip on dimmer switches?
Triac-based leading-edge dimmer switches chop the AC sine wave, creating massive $dv/dt$ and $di/dt$ transients every half-cycle. These sharp edges contain broad-spectrum high-frequency energy that easily passes through the $N_{HPF}$ node and triggers the envelope detector. In commercial UL 1699 listed breakers, the DSP employs digital notch filters and masking windows that ignore the specific phase-angles where the dimmer is known to fire. If your ESP32 prototype is tripping on dimmers, you must implement a software 'blanking window' in your code that ignores ADC spikes occurring within the first 2 milliseconds of the half-cycle zero-crossing.
