A listed combination-type arc-fault circuit interrupter (AFCI) does not simply measure RMS current; it relies on an embedded Digital Signal Processor (DSP) or high-speed microcontroller to sample high-frequency current noise (typically 10 kHz to 100 kHz) and distinguish harmless switching transients from dangerous series and parallel arcs. The analog front-end topology conditioning this signal before it hits the MCU’s ADC is the critical bottleneck of the entire safety device. If the front-end clips, saturates, or filters out the arc signature, the DSP is blind, and the breaker fails to trip.
This guide breaks down the embedded sensing topology of a modern combination-type AFCI, provides real component values for the analog conditioning stage, and outlines how to breadboard-test the signal chain safely on the bench.
Embedded Sensing Topology and Node Definitions
To detect an arc, the microcontroller must "see" the high-frequency broadband noise generated by the plasma gap. A purely analog RMS-to-DC converter will miss the high-frequency "shoulders" of a series arc. Therefore, modern listed combination-type AFCIs use an active analog front-end feeding a high-speed ADC, allowing the firmware to run a Fast Fourier Transform (FFT) or zero-crossing variance algorithm.
The signal chain is defined by four critical nodes:
- Node 1 ($V_{CT}$): Current Transformer Secondary. A toroidal CT clamps around the line/neutral conductors, outputting a scaled-down AC current proportional to the load.
- Node 2 ($V_{HPF}$): High-Pass Filter Output. A passive RC network strips away the 60 Hz fundamental and low-frequency inrush currents, passing only the >5 kHz arc noise.
- Node 3 ($V_{AMP}$): Non-inverting Op-Amp Output. A rail-to-rail operational amplifier boosts the microvolt-level high-frequency noise to a level readable by the MCU.
- Node 4 ($V_{ADC}$): Microcontroller ADC Input. The conditioned, biased signal enters the DSP for digital sampling (typically at 200+ kSPS).
Why this topology over the alternative? Older "branch/feeder-only" AFCIs used simpler diode-bridge peak detectors that only tripped on high-amplitude parallel arcs (line-to-neutral shorts). They were blind to series arcs (a broken wire in a cord), which draw normal load current but generate high-frequency noise. The active analog + DSP topology is mandatory for a combination-type listing (per UL 1699 and NEC Article 210.12) because it preserves the high-frequency signature of series arcs without being blinded by the 60 Hz load current.
| Component | Value / Part Number | Tolerance / Rating | Node | Function in Topology |
|---|---|---|---|---|
| Toroidal CT | 1:2000 Turns Ratio | 10mA - 20A Primary | Node 1 | Steps down 20A mains to 10mA secondary current. |
| Burden Resistor | 47 Ω | 1%, 0.25W Metal Film | Node 1 | Converts CT secondary current to voltage (~470mV peak at 20A). |
| Coupling Capacitor | 100 nF | X7R Ceramic, 50V | Node 2 | Blocks DC offset and forms high-pass filter with pull-down. |
| High-Pass Resistor | 10 kΩ | 1%, 0.1W | Node 2 | Sets HPF cutoff to ~160 Hz, stripping 60 Hz fundamental. |
| Op-Amp | MCP6002-I/P | Rail-to-Rail I/O, 1MHz GBW | Node 3 | Amplifies high-frequency noise by ~10x (Gain = 1 + Rf/Rg). |
| Feedback Network | 47 kΩ / 5.1 kΩ | 1% Metal Film | Node 3 | Sets non-inverting gain to ~10.2x. |
| ADC Bias Divider | 10 kΩ / 10 kΩ | 1% | Node 4 | Biases AC signal to VCC/2 (1.65V) for unipolar MCU ADC. |
Node Behavior and Failure Extremes
When designing or troubleshooting the sensing stage of a listed combination-type arc-fault circuit interrupter, understanding how component degradation affects the DSP's input is critical. A shifted cutoff frequency or a saturated op-amp will cause nuisance tripping or, worse, a failure to trip during an actual fire hazard.
| Element Changed / Failed | Effect on Node Behavior | Extreme Failure Mode (Open/Short) |
|---|---|---|
| CT Burden Resistor (Open) | Node 1 voltage drops to zero; DSP sees no load or noise. | Open: CT secondary has infinite impedance. Core saturates, inducing lethal kV spikes that will arc internally and destroy the op-amp input stage. |
| Coupling Cap (Shorted) | Node 2 passes the 60 Hz fundamental. Signal amplitude spikes. | Short: 60 Hz mains hum passes directly to the op-amp. The amplifier clips against the rails, the ADC saturates, and the DSP ignores the HF arc signature. |
| High-Pass Resistor (Drift High) | HPF cutoff frequency drops; more 60 Hz bleed-through reaches Node 3. | Open: Node 2 floats. The op-amp input bias current pulls the pin to the rail, causing a permanent false-trip signal at the ADC. |
| Op-Amp Feedback Resistor (Short) | Gain drops to 1 (unity). High-frequency arc noise is too small for the ADC to resolve. | Short: DSP cannot distinguish arc noise from baseline ADC quantization noise. Breaker fails to trip on series arcs (violating combination-type listing). |
Breadboard-Testing the Arc Signature Front-End
You cannot safely inject real arc noise into a bench setup without specialized high-voltage carbon-rod arc generators (as specified in UL 1699 testing protocols). However, you can validate the analog front-end topology by simulating the CT output using a microcontroller's DAC or a function generator.
Here is the step-by-step bench procedure to verify the signal conditioning before writing the DSP interrupt code:
- Build the HPF Stage: On a solderless breadboard, wire the 100 nF coupling capacitor in series with the 10 kΩ high-pass resistor to ground. Connect the junction to the non-inverting input of the MCP6002 op-amp.
- Inject the Simulated Signal: Use an ESP32’s internal DAC (or a bench function generator) to generate a composite waveform: a 1 Vpp 60 Hz sine wave with a 20 mVpp 50 kHz square wave superimposed. This simulates a 15A load with a series arc noise burst.
- Measure Node 2 (HPF Out): Connect an oscilloscope probe to Node 2. You should see the 60 Hz fundamental attenuated by at least -20 dB, while the 50 kHz "arc noise" passes through at nearly full amplitude.
- Verify Amplification at Node 3: Probe the op-amp output. The 50 kHz burst should now be amplified to ~200 mVpp, riding on a 1.65V DC bias (set by your voltage divider). Ensure the op-amp is not clipping against the 3.3V rail during high-load simulation.
- Sample with the MCU: Connect Node 4 to the ESP32’s ADC1 channel. Write a simple interrupt-driven sampling loop running at 250 kSPS. Feed the samples into an FFT library (like ArduinoFFT). You should see a distinct, dominant frequency bin at 50 kHz, proving the DSP can isolate the arc signature from the load current.
Why Combination-Type Over Branch-Only AFCI?
When specifying or reverse-engineering these devices, it is vital to understand why the combination-type topology is the modern standard. Early AFCIs (Branch/Feeder type) only monitored for parallel arcs—massive current spikes caused by line-to-neutral or line-to-ground faults. They relied on simple current magnitude thresholds and basic high-frequency filtering.
However, electrical fire statistics show that many residential fires start from series arcs: a frayed lamp cord, a loose screw terminal on a receptacle, or a broken wire inside a wall. A series arc does not draw excess current; it draws the normal load current of the appliance (e.g., 5A for a TV). A branch-only AFCI sees 5A and assumes everything is fine.
A listed combination-type arc-fault circuit interrupter solves this by analyzing the shape of the current waveform. The embedded DSP looks for the characteristic "flat spots" (current zero-crossings where the arc plasma extinguishes and reignites) and the broadband RF noise injected into the line. By utilizing the high-speed ADC and active analog front-end detailed above, the combination-type breaker detects the series arc signature even when the total RMS current is well below the breaker's 15A or 20A trip threshold, providing comprehensive protection that older topologies simply cannot achieve.
