Successive ADC Explained: How SAR Converters Digitize Signals in Embedded Systems

A successive approximation register (SAR) ADC digitizes an analog voltage by using a binary search algorithm, iteratively comparing the input signal against an internal digital-to-analog converter (DAC) until it zeroes in on the exact digital value. If you have ever read a potentiometer on an Arduino Uno, sampled a current shunt on an STM32, or wired up an external MCP3208 chip, you have relied on a successive ADC. Unlike simpler integrating converters or ultra-fast flash ADCs, the SAR architecture dominates the embedded space because it offers the perfect middle ground: medium-to-high resolution (10 to 18 bits) at moderate speeds (10 kSPS to 5 MSPS) with very low power consumption.

The Binary Search Engine: How a Successive ADC Actually Works

Think of a successive ADC like playing a "guess the number" game. If I ask you to guess a number between 1 and 1,000, you would not start at 1 and count up. You would ask, "Is it higher or lower than 500?" Based on the answer, you eliminate half the possibilities and guess 250 or 750 next. A SAR ADC does exactly this with voltage.

Inside the silicon, the ADC uses a sample-and-hold circuit to freeze the incoming analog voltage. It then uses an internal DAC to generate a reference voltage, starting at exactly half of the full-scale range. A high-speed comparator checks if the input voltage is higher or lower than the DAC output, setting the Most Significant Bit (MSB) to 1 or 0. It then repeats this process for the next bit, adding or subtracting half of the previous step size, until every bit is resolved.

SAR ADC Specifications: What the Datasheet Actually Means

When selecting a microcontroller or an external ADC IC, the resolution (bit count) is only half the story. You must evaluate the sample rate, Integral Non-Linearity (INL), and the interface overhead. Below is a specification comparison of common SAR ADCs you will encounter on the bench.

Reading the INL: Integral Non-Linearity tells you how much the actual transfer function deviates from a perfect straight line. An INL of ±3 LSB on the STM32F4 means your 12-bit reading could be off by up to 3 steps purely due to silicon imperfections, effectively reducing your true precision to about 11.5 bits unless you apply software calibration.

Where You Meet Successive ADCs in Practice

Understanding that an ADC uses a successive approximation register fundamentally changes how you design your analog front-end circuit. The most critical real-world implication of a SAR ADC is its switched-capacitor input architecture.

When the SAR ADC initiates a sample, an internal switch closes to connect the input pin to a tiny internal sampling capacitor (usually between 10pF and 50pF). This capacitor must charge to the exact input voltage before the switch opens and the binary search begins. If your external signal source has a high impedance (e.g., a 100kΩ voltage divider), it cannot supply the sudden spike of current needed to charge that capacitor in time. The voltage at the pin sags, and your ADC reads artificially low.

The ESP32 SAR ADC Quirks

If you work with Espressif hardware, you will interact with the ESP32 internal SAR ADCs. While they are technically 12-bit SAR converters, they are notorious in the maker community for non-linearity and noise. Because the SAR switching noise couples into the Wi-Fi/Bluetooth RF subsystem, using ADC2 while Wi-Fi is active will return garbage data. Furthermore, the ESP32's SAR ADC exhibits a dead zone near 0V and 3.3V. For precision analog work on an ESP32, bypass the internal SAR entirely and use an external I2C/SPI Sigma-Delta ADC like the ADS1115.

What People Commonly Confuse It With

Makers frequently confuse SAR ADCs with Sigma-Delta (ΣΔ) ADCs.

• SAR ADCs are your workhorses for general-purpose embedded sensing: motor control feedback, battery voltage monitoring, and joystick inputs. They offer instant, single-shot conversions with low latency.
• Sigma-Delta ADCs (like the ADS1115 or HX711) use oversampling and digital filtering to achieve massive resolution (16 to 24 bits) but at very slow speeds (10 to 860 SPS). You use Sigma-Delta for load cells, RTD temperature sensors, and audio, where you need extreme precision but do not care about microsecond latency.

Troubleshooting SAR ADC Readings: Noise, Glitches, and Impedance

When your successive ADC readings are jumping around or consistently offset, the issue is almost always in the analog front-end, not the digital code. Follow this decision path to isolate the fault.

1. Symptom: Readings are always lower than the multimeter shows.
   Cause: Source impedance is too high, causing voltage droop during the sampling phase.
   Fix: Measure the Thevenin equivalent resistance of your sensor network. If it exceeds 10kΩ, add a 100nF X7R capacitor between the ADC pin and GND. Avoid Y5V capacitors; their capacitance drops drastically under DC bias.
2. Symptom: Readings fluctuate randomly by ±10 to 20 LSBs.
   Cause: High-frequency noise aliasing into the sampling window, or a noisy voltage reference.
   Fix: Implement a hardware RC low-pass filter (e.g., 100Ω resistor in series, 1µF capacitor to ground) giving a cutoff frequency well below your Nyquist limit. Ensure your VREF is driven by a dedicated low-noise LDO (like the LP5907), not the noisy digital 3.3V rail.
3. Symptom: Reading one analog pin affects the reading on the next pin (Ghosting).
   Cause: The internal sampling capacitor did not have enough time to discharge/charge between multiplexer channel switches.
   Fix: Increase the ADC acquisition time (sample-and-hold time) in your microcontroller's register settings, or read the pin twice in software and discard the first value.