The XOR (Exclusive OR) gate outputs a HIGH signal only when its inputs differ. In the US (IEEE/ANSI Y32.2), the XOR gate symbol is a D-shape with a curved back and a secondary detached curved line at the inputs. In Europe and international standards (IEC 60617), it is drawn as a rectangle containing the text "=1". Below is the complete reference for schematic symbols, regional standards, and physical IC pinouts.
| Standard | Visual Shape | Internal Text / Qualifier | Primary Region | XNOR Variant Difference |
|---|---|---|---|---|
| IEEE / ANSI Y32.2 | D-shape with curved back | Detached curved line near inputs | North America, Japan | Adds an inversion bubble on the output |
| IEC 60617 | Rectangular box | "=1" | Europe, UK, AU, International | Adds an inversion bubble or a right-side slash |
| DIN 40700 (Legacy) | Rectangular with rounded right edge | "=1" or specialized parity mark | Germany (Pre-1990s legacy) | Output line originates from a small semicircle |
| MIL-STD-806B | Identical to IEEE/ANSI | Detached curved line | US Military / Aerospace | Often includes explicit pin numbers inside the shape |
Standard Variants: Decoding the XOR Gate Symbol
When reading schematics, the standard used depends heavily on the origin of the design software and the engineering team's regional training. Understanding the nuance of each prevents miswiring during PCB layout or breadboard prototyping.
The IEEE/ANSI Shape (US Standard)
The standard US XOR symbol looks like an OR gate (a D-shape with a curved input side and a pointed output), but with an additional curved line drawn parallel to the input side, separated by a small gap. This detached line is the exclusive qualifier. It tells the reader: "This is not a standard inclusive OR; it requires exclusive inputs." If you see the D-shape without the detached line, it is a standard OR gate. If you see an AND gate shape (straight back, flat inputs) with a detached line, it is a rare XAND (which is logically equivalent to XNOR, but almost never used in modern schematics).
The IEC 60617 Shape (International Standard)
The IEC standard abandons unique shapes for every logic function in favor of uniform rectangles. The logic function is defined entirely by the text inside the box. For a 2-input XOR gate, the symbol is a rectangle with "=1" inside. This literally translates to "the output is HIGH if exactly 1 input is HIGH."
Note on 3-input XOR gates: Under IEC standards, a 3-input XOR is technically an odd-parity generator. The symbol will often read "2k+1" or "ODD" instead of "=1", meaning the output is HIGH if an odd number of inputs (1 or 3) are HIGH. The IEC 60617 standard reference strictly defines these parity qualifiers to avoid ambiguity in complex logic arrays.
Real-World IC Pinouts and Bench Testing
Schematics only get you so far; eventually, you have to wire the physical silicon. The two most common quad 2-input XOR ICs you will encounter on the bench are the TTL-compatible 74HC86 and the CMOS CD4070. Both use a standard 14-pin DIP (Dual In-line Package) footprint, but their internal architectures and voltage tolerances differ drastically.
| Pin Number | Function (74HC86 / CD4070) | Gate Assignment | Bench Testing Note |
|---|---|---|---|
| 1, 2 | 1A, 1B (Inputs) | Gate 1 | Float tolerance differs (see warning below) |
| 3 | 1Y (Output) | Gate 1 | Source/Sink current limits apply here |
| 4, 5 | 2A, 2B (Inputs) | Gate 2 | Tie to GND if unused |
| 6 | 2Y (Output) | Gate 2 | Do not backfeed voltage into output |
| 7 | GND (74HC86) / VSS (CD4070) | Power Return | Must be tied to circuit common |
| 8, 9 | 3Y (Output), 3A, 3B (Inputs) | Gate 3 | Pin 8 is output, 9/10 are inputs |
| 11, 12, 13 | 4B, 4A (Inputs), 4Y (Output) | Gate 4 | Pin 13 is output |
| 14 | VCC (74HC86) / VDD (CD4070) | Positive Supply | 2V-6V (74HC) / 3V-15V (CD40) |
If you are using the CD4070 (or any 4000-series CMOS), never leave unused inputs floating. Unlike the 74HC86, which has internal pull-ups that default floating TTL inputs to a HIGH state, CMOS inputs have near-infinite impedance. A floating CMOS input will act as an antenna, pick up ambient RF noise, and cause the internal output transistors to rapidly toggle. This creates a direct shoot-through current path from VDD to VSS, causing the IC to overheat and physically crack or melt. Always tie unused CMOS inputs directly to GND or VDD.
Truth Table & Logic Verification
When verifying a circuit, map the physical pins to the logical truth table. According to the All About Circuits digital logic chapter, the XOR function is mathematically equivalent to modulo-2 addition.
- 0, 0 → 0: Both inputs LOW, output LOW.
- 0, 1 → 1: Inputs differ, output HIGH.
- 1, 0 → 1: Inputs differ, output HIGH.
- 1, 1 → 0: Both inputs HIGH, output LOW.
The "Rows People Get Wrong" and Faded Marking Recovery
Whether you are grading an exam, reviewing a junior engineer's schematic, or salvaging parts, specific rows in logic tables and symbol charts consistently cause errors.
Schematic and Truth Table Rows People Get Wrong
- The IEC "=1" Misinterpretation: Beginners frequently look at the IEC rectangular symbol with "=1" and assume it represents an analog voltage comparator or an equality checker (outputting HIGH when Input A equals Input B). In reality, an equality checker is an XNOR gate. The "=1" strictly means "the sum of the HIGH inputs equals exactly 1".
- The IEEE Detached Line: In hand-drawn schematics or low-resolution PDF prints, the detached curved line of the IEEE XOR symbol often gets merged with the main D-shape body, making it look like a standard OR gate, or it gets mistaken for a parallel capacitor. Always verify the logic by checking the part number in the BOM (Bill of Materials) if the symbol is ambiguous.
- The 1,1 Truth Table Row: In standard OR gates, 1+1=1. In XOR gates, 1+1=0. When cascading XOR gates for parity checking, engineers sometimes forget that the 1,1 row resets the output to LOW, which is the exact mechanism that allows XOR gates to detect single-bit errors in data transmission.
Recovering Faded or Missing IC Markings
If you are harvesting components from a salvaged PCB and find a 14-pin DIP with faded laser etching, you can safely identify if it is a 74HC86 or CD4070 without guessing. You can reference the Texas Instruments SN74HC86 product page for specific electrical characteristics, but here is the bench procedure:
- Visual Inspection: Look for a manufacturer logo. TI, NXP, and ON Semi usually mark the 74-series. RCA, Fairchild, or ST usually mark the 4000-series CMOS.
- Multimeter Diode Test: Set your DMM to diode mode. Place the black probe on Pin 7 (GND) and touch the red probe to Pin 1 (Input). A 74HC86 will typically show a forward voltage drop of ~0.6V to ~0.7V due to the internal input protection diodes to VCC/GND. A CD4070 will typically read "OL" (Open Loop) or show a much higher threshold because its protection network is structured differently.
- Live Logic Probe Test: If the IC is still soldered to a powered board, use a logic probe or a DMM on DC voltage. Toggle the inputs of a single gate (e.g., Pins 1 and 2). If the output (Pin 3) flips HIGH only when the inputs are in opposite states, you have confirmed an XOR function. Measure the VCC rail: if it is running at 12V, it is almost certainly a CD4070 (CMOS). If it is running at 5V or 3.3V, it is likely a 74HC86 or 74LS86.
By anchoring your knowledge to the exact standard (IEEE vs IEC) and understanding the physical silicon limitations (TTL vs CMOS), you eliminate the guesswork from digital logic design and troubleshooting.
