Translating an SMPS power supply schematic from a datasheet reference design to a working board for a 24V battery bank requires more than just copying component values. You have to account for the brutal reality of solar charge profiles, voltage spikes, and thermal derating. When stepping down a 24V nominal system (which actually swings from 21V to nearly 29V) to a stable 12V rail for lighting or pumps, the topology you choose dictates your system's reliability.
Linear vs. Switching: The Dropout and Thermal Reality
The most common mistake in low-power auxiliary circuits is defaulting to a linear regulator (LDO) because the schematic is simple. For a 24V-to-12V step-down, a linear regulator is a thermal disaster. Let's run the dropout and headroom math.
A 24V nominal lead-acid or LiFePO4 battery bank actually operates between 21.0V (discharged) and 28.8V (absorption/charge peak). A standard linear regulator requires 2V to 3V of headroom to maintain regulation. This means your 12V output will drop out and collapse when the battery voltage falls below 14V—long before the battery is actually empty.
More critically, look at the heat dissipation at the top of the charge cycle. At 28.8V input and a 5A load, the voltage dropped across the linear pass transistor is 16.8V.
Linear Heat Dissipation: P = Vdrop × I = 16.8V × 5A = 84 Watts.
You would need a massive heatsink and active cooling just to step down to 12V. A switching regulator (SMPS), by contrast, operates at roughly 92% efficiency. For a 60W output (12V × 5A), the input power is ~65.2W, meaning total heat dissipation is only 5.2 Watts—easily managed by the IC's exposed thermal pad and PCB copper.
| Topology | Efficiency | Heat Profile | Noise / EMI | Relative Cost |
|---|---|---|---|---|
| Linear (LDO) | ~41% | Extreme (Requires massive heatsinks) | Zero switching noise | Low ($0.50 - $1.50) |
| Non-Sync Buck | 82% - 88% | Moderate (Diode forward drop causes heat) | Medium (Switching node ringing) | Medium ($2.00 - $4.00) |
| Synchronous Buck | 90% - 95% | Low (MOSFET Rds(on) minimizes loss) | Medium-High (Fast dV/dt edges) | High ($4.00 - $8.00) |
| Flyback (Isolated) | 75% - 85% | Moderate (Transformer core/copper loss) | High (Leakage inductance spikes) | Highest ($6.00 - $12.00) |
For a high-current 24V DC bus, a synchronous buck converter is the undisputed winner, trading a slightly higher component cost for massive thermal savings and extended battery runtime.
Anatomy of a 24V-to-12V SMPS Power Supply Schematic
Let's break down a practical, robust SMPS power supply schematic designed to step a 24V solar battery bank down to 12V at 5A. We will use the Texas Instruments TPS54560, a wide-input (4.5V to 60V) synchronous buck controller built specifically for harsh automotive and solar environments.
Input Protection and Range
Solar charge controllers and inductive loads (like water pumps switching off) generate severe voltage transients. Your input stage must survive a 60V load dump.
- Reverse Polarity: Use a P-Channel MOSFET (e.g., SiS443DN) driven by an NPN transistor. This provides reverse polarity protection with only a ~20mV drop, unlike a Schottky diode which would waste 2.5W at 5A.
- Transient Suppression: Place a TVS diode (SMAJ36A) directly across the input terminals to clamp inductive spikes before they reach the SMPS IC.
- Input Capacitance: Use two 10µF, 100V X7R ceramic capacitors placed as close to the VIN and PGND pins as possible to supply high-frequency switching current.
Power Stage Component Values
The core of the SMPS schematic relies on calculating the inductor and feedback network for your specific target voltage and switching frequency (set to 400kHz via a 130kΩ RT resistor to the AGND pin).
| Component | Reference Designator | Value / Specification | Purpose |
|---|---|---|---|
| Inductor | L1 | 10µH, Shielded, 8A Isat | Energy storage; sized for 30% ripple current |
| Output Caps | C_OUT1, C_OUT2 | 2x 100µF, 25V X7R Ceramic | High-frequency ripple filtering |
| Bulk Cap | C_OUT3 | 470µF, 25V Polymer Electrolytic | Load transient response and bulk storage |
| Bootstrap Cap | C_BOOT | 100nF, 16V X7R Ceramic | Drives the high-side MOSFET gate |
| Feedback R1 (Top) | R_FBT | 140kΩ, 1% tolerance | Sets output voltage divider |
| Feedback R2 (Bot) | R_FBB | 10kΩ, 1% tolerance | Sets output voltage divider |
Feedback Math: The TPS54560 uses a 0.8V internal reference. The output voltage is calculated as Vout = 0.8V × (1 + RFBT / RFBB). Using 140kΩ and 10kΩ yields exactly 12.0V. Always use 1% tolerance resistors here; a 5% drift on a 10kΩ resistor can push your 12V rail out of spec for sensitive microcontrollers.
Thermal Management and Derating in Practice
An SMPS power supply schematic is only as good as its PCB layout. The TPS54560 features an exposed thermal pad on the bottom of the IC. If you route this to a standard 1oz copper pour on a 2-layer board, the thermal resistance (θJA) will be too high, and the IC will trigger its internal thermal shutdown at roughly 3A of continuous load.
To achieve the full 5A rating, the layout must include a multi-layer thermal via array directly under the IC pad, stitching to a solid ground plane on the bottom layer. According to buck converter layout guidelines, keeping the SW (switch node) copper area as small as possible while maintaining adequate current width reduces radiated EMI without sacrificing thermal mass.
Ripple and Noise Expectations
With a 10µH inductor and 400kHz switching frequency, the peak-to-peak inductor ripple current is roughly 1.5A. Because we are using low-ESR X7R ceramics (typically ~3mΩ ESR) in parallel with a polymer bulk cap, the expected output voltage ripple is exceptionally low: roughly 15mV to 25mV peak-to-peak.
Do not use a standard oscilloscope probe with a 6-inch ground lead alligator clip to measure SMPS ripple. The loop area will act as an antenna, picking up the switching node's magnetic field and showing 500mV of "noise" that isn't actually on the rail. Use a coaxial pigtail or a probe tip-and-barrel adapter to measure directly across the output capacitor terminals.
Thermal Derating Curve
Even with optimal layout, ambient temperature dictates your maximum continuous current. In an enclosed solar charge box where ambient temperatures can reach 55°C in the summer, you must apply derating. For this specific design, expect a 15% reduction in maximum continuous current for every 10°C rise above 40°C ambient. If your enclosure hits 60°C, design your downstream loads to pull no more than 4A to maintain a safe safety margin below the IC's thermal trip point.
SMPS Power Supply Schematic FAQs
How do I calculate the feedback resistor values for my SMPS power supply schematic?
Locate the internal reference voltage (Vref) in the IC's datasheet—usually 0.6V, 0.8V, or 1.2V. The formula is Vout = Vref × (1 + R1 / R2). Pick a standard value for R2 (usually between 10kΩ and 49.9kΩ to minimize quiescent current draw while avoiding noise susceptibility), then solve for R1: R1 = R2 × ((Vout / Vref) - 1). Always select the closest standard 1% E96 series resistor value and verify the final voltage with a spreadsheet.
Why does my SMPS power supply schematic require a bootstrap capacitor?
A synchronous buck converter uses a high-side N-channel MOSFET because it offers vastly lower Rds(on) than a P-channel MOSFET. However, to turn an N-channel MOSFET on, its gate voltage must be driven 5V to 10V above its source pin. When the high-side FET turns on, its source pin jumps to the input voltage. The bootstrap capacitor (typically 100nF to 1µF) acts as a floating charge pump, storing energy during the low-side FET's conduction phase and providing the necessary gate-drive voltage above the input rail when the high-side FET switches on.
What is the difference between synchronous and non-synchronous SMPS topologies?
In a non-synchronous buck converter, a Schottky diode acts as the freewheeling path when the main switch turns off. Diodes have a fixed forward voltage drop (0.3V to 0.5V), which generates significant heat at high currents. A synchronous topology replaces that diode with a second, actively controlled N-channel MOSFET. Because a MOSFET's voltage drop is based on its Rds(on) (often just 10mΩ to 30mΩ), conduction losses plummet, pushing efficiency from ~85% up to 94% or higher, especially at low output voltages and high currents.
How do I reduce high-frequency switching noise in an SMPS layout?
High-frequency ringing (often 50MHz to 150MHz) is caused by parasitic inductance in the high di/dt switching loop. To minimize this, the physical loop formed by the input capacitor, the high-side MOSFET, the low-side MOSFET, and the ground return must be as physically small as possible. Place the input ceramic capacitor directly adjacent to the IC's VIN and PGND pins, using wide, short traces. Avoid routing the switching node (SW) under the feedback trace, as capacitive coupling will inject noise directly into your voltage regulation loop.
