When designing auxiliary power rails for a 24V nominal solar charge controller or battery management system (BMS) telemetry board, you need to step down a wide, noisy battery voltage to clean 5V and 3.3V logic rails. For a typical load of 5V at 1.5A (relays, microcontrollers) and 3.3V at 300mA (ESP32, precision ADCs), the definitive power supply IC combination is the Texas Instruments TPS5430DDA (buck converter) followed by a Diodes Inc. AP2112K-3.3 (low-dropout regulator). This pairing handles the wide 18V–32V input range, manages thermal dissipation without massive heatsinks, and isolates switching noise from sensitive RF and sensor circuits.

Linear vs. Switching Topologies for Battery-Powered Loads

The first decision in any power supply IC selection is topology. In battery-powered telemetry systems, every milliamp of wasted quiescent current and every watt of burned heat matters. Here is how linear regulators (LDOs) and switching regulators (bucks) stack up for a 24V-to-5V conversion.

Criteria Linear Regulator (LDO) Switching Regulator (Buck)
Efficiency ~15% (Vout/Vin = 5V/32V) 85% – 92%
Heat Dissipation (1.5A load) 40.5W (Requires massive heatsink) ~0.8W (Handled by PCB copper)
Output Noise Microvolts (µV) - Extremely clean Millivolts (mV) - Switching ripple present
BOM Cost & Footprint Low cost, tiny (SOT-23), no inductor Higher cost, larger (needs inductor/caps)
Warning: Never use a linear regulator to drop 24V nominal (up to 32V fully charged) down to 5V for loads exceeding 50mA. The thermal dissipation will instantly trigger the LDO's internal thermal shutdown, or worse, melt the solder joints on your PCB.

The Decision Tree: Picking Your Power Supply IC

Use this decision matrix to select the right topology and terminate on a concrete part number for your specific board section.

Condition / Load Profile Topology Choice Concrete Default Pick
Load > 300mA OR (Vin - Vout) > 3V Switching Buck TPS5430DDA (up to 3A, 36V max Vin)
Load < 100mA AND (Vin - Vout) < 2V Linear LDO AP2112K-3.3 (600mA, low noise)
Highly noise-sensitive (12-bit+ ADC, RF) Buck + Post-LDO TPS5430 (to 5V) → AP2112 (to 3.3V)
Input > 60V (48V nominal battery banks) Wide-Vin Switching Buck LM5164 (up to 100V Vin, 1A out)

Design Example: 24V Nominal Input to 5V/3.3V Rails

Let's engineer the power path for a BMS telemetry board. The input is a 24V nominal lithium iron phosphate (LiFePO4) battery bank, which swings from 20V (discharged) to 28.8V (absorption charge), with transient spikes up to 32V. We need a 5V rail at 1.5A for relays and a 3.3V rail at 300mA for an ESP32-WROOM-32.

Stage 1: The 5V Buck Converter (TPS5430DDA)

The TPS5430 is a workhorse power supply IC for wide-input DC systems. We must verify the minimum on-time to ensure the IC can physically achieve the low duty cycle required at maximum input voltage.

  • Target Duty Cycle: $D = \frac{V_{out}}{V_{in}} = \frac{5V}{32V} = 15.6\%$
  • Required On-Time: $t_{on} = \frac{D}{f_{sw}} = \frac{0.156}{500kHz} = 312ns$
  • Datasheet Min On-Time: 200ns. Since 312ns > 200ns, the IC will regulate perfectly without pulse-skipping.

Recommended BOM Values:

  • Inductor: 15µH shielded ferrite (e.g., Wurth 74477420). Keeps ripple current around 30% of max load.
  • Output Capacitor: 68µF low-ESR ceramic or polymer. Do not use standard electrolytic here; the ESR is too high to filter 500kHz ripple effectively.
  • Boot Capacitor: 100nF (0.1µF) X7R ceramic, placed as close to the BOOT and PH pins as physically possible.

Stage 2: The 3.3V LDO (AP2112K-3.3)

Feeding the ESP32 directly from the 5V buck is risky; the 500kHz switching ripple can couple into the ESP32's internal ADC and degrade Wi-Fi receiver sensitivity. We drop the 5V rail to 3.3V using an LDO.

  • Dropout Voltage Check: The AP2112 has a maximum dropout of 250mV at 300mA. Our headroom is $5V - 3.3V = 1.7V$. Since 1.7V > 0.25V, the LDO is fully in regulation.
  • Power Dissipation: $P_{diss} = (V_{in} - V_{out}) \times I_{load} = (5V - 3.3V) \times 0.3A = 0.51W$.
Pro-Tip: A standard SOT-23-5 package has a thermal resistance ($\theta_{JA}$) of ~150°C/W. Dissipating 0.51W would raise the junction temp by 76°C, pushing it dangerously close to thermal shutdown on a hot summer day inside an enclosure. Always specify the SOT-223 package variant for this LDO, which drops $\theta_{JA}$ to ~50°C/W, resulting in a safe 25.5°C temperature rise.

Thermal Derating and Input Protection

Battery environments are electrically hostile. Load dumps from disconnecting cables and inductive kickback from nearby charge controllers will destroy an unprotected power supply IC.

Input Protection Circuit

  1. TVS Diode: Place an SMBJ28A bidirectional TVS diode across the input terminals. It clamps transients at 28.8V, well below the TPS5430's 36V absolute maximum rating.
  2. Reverse Polarity: Avoid standard Schottky diodes (like the SS34) for reverse polarity protection on the main input; they drop ~0.5V, wasting power and generating heat. Instead, use a P-channel MOSFET (e.g., SI2301) configured as an ideal diode. It drops only $I^2R$ losses (roughly 20mV at 1.5A).
  3. Overcurrent: A 2A resettable PTC fuse (e.g., Bourns MF-MSMF200) upstream of the TVS prevents a dead short from pulling the battery bus to zero and resetting your main inverter.

Thermal Derating the Buck IC

The TPS5430DDA features an exposed thermal pad (PowerPAD). Assuming 85% efficiency at full 1.5A load, the IC dissipates roughly 1.3W. With a $\theta_{JA}$ of 40°C/W on a standard 2-layer PCB with adequate copper pour under the pad, the junction temperature rise is $1.3W \times 40°C/W = 52°C$. At a worst-case ambient enclosure temperature of 50°C, the silicon junction sits at 102°C—comfortably below the 125°C thermal shutdown threshold.

Ripple, Noise, and Layout Expectations

Understanding the noise profile of your chosen power supply IC dictates your PCB layout and filtering strategy. According to Analog Devices' guidelines on DC/DC conversion, switching ripple is a function of output capacitance and ESR, while radiated noise is a function of loop area.

Buck Converter Ripple Math

For the TPS5430 running at 500kHz with a 15µH inductor and 68µF ceramic output capacitor (ESR ~3mΩ):

  • Inductor Ripple Current ($\Delta I_L$): ~450mA peak-to-peak.
  • Capacitive Ripple: $\Delta V_C = \frac{\Delta I_L}{8 \cdot f_{sw} \cdot C_{out}} \approx 3.3mV$.
  • ESR Ripple: $\Delta V_{ESR} = \Delta I_L \cdot ESR = 0.45A \cdot 0.003\Omega = 1.35mV$.
  • Total Expected Ripple: ~5mV to 10mV peak-to-peak on the 5V rail. This is excellent for digital logic, but still too noisy for a 12-bit ADC reference.

LDO Power Supply Rejection Ratio (PSRR)

This is where the AP2112 earns its keep. The AP2112 datasheet specifies a Power Supply Rejection Ratio (PSRR) of 70dB at 1kHz, and roughly 50dB at the 500kHz switching frequency of the buck. A 50dB rejection means the 10mV of 500kHz ripple on the 5V rail is attenuated by a factor of 316, resulting in a microscopic ~31µV of ripple on the 3.3V rail. This guarantees clean power for the ESP32's RF frontend and any external I2C temperature sensors.

Layout Rule of Thumb: Keep the high-di/dt switching loop (Input Cap $\rightarrow$ High-Side MOSFET $\rightarrow$ Inductor $\rightarrow$ Low-Side MOSFET $\rightarrow$ back to Input Cap ground) as tight as physically possible. Route the feedback resistor network for the buck directly from the output capacitor pad to the VSENSE pin, avoiding any vias that could inject switching noise into the feedback node.