The NOR logic gate is a fundamental digital building block that outputs a HIGH signal only when all of its inputs are LOW. On a schematic, the NOR symbol is essentially an OR gate with an inversion bubble on the output. However, how that symbol is drawn—and how the physical integrated circuit (IC) is pinned out—varies significantly depending on the drafting standard and the specific silicon family you are holding. This reference provides the exact symbols, truth tables, and pinouts you need to read legacy schematics and wire modern prototype boards without frying your logic ICs.
NOR Logic Gate Symbols and Truth Tables
Before you trace a circuit, you need to know which drafting standard the engineer used. The two dominant standards are the US-centric ANSI/IEEE distinctive shapes and the international IEC rectangular outlines. Below is the definitive comparison of how the NOR symbol is represented across regions and eras.
| Standard | Visual Shape | Output Indicator | Region / Era |
|---|---|---|---|
| ANSI/IEEE Std 91 | Distinctive shape: Curved back, pointed front (like a D with a curved left edge) | Small circle (bubble) on the output line | US, Canada, legacy global schematics |
| IEC 60617 | Rectangular box with the qualifier ≥1 inside |
Small circle (bubble) on the output line | EU, UK, modern international designs |
| DIN 40900 | Rectangular box with the number 1 inside |
Overline above the output pin number/text | Obsolete (Historical German/European) |
The 2-Input NOR Truth Table
Regardless of the symbol used on the schematic, the underlying Boolean logic remains identical. The Boolean expression for a 2-input NOR gate is Y = NOT (A OR B), often written as Y = (A + B)' or Y = A ↓ B (Peirce arrow).
| Input A | Input B | Output Y | Practical State |
|---|---|---|---|
| LOW (0) | LOW (0) | HIGH (1) | Only condition for HIGH output |
| LOW (0) | HIGH (1) | LOW (0) | Output pulled to ground |
| HIGH (1) | LOW (0) | LOW (0) | Output pulled to ground |
| HIGH (1) | HIGH (1) | LOW (0) | Output pulled to ground |
≥1 qualifier with an AND gate. Remember: ≥1 means 'one or more inputs HIGH triggers the OR function'. The AND gate uses the & qualifier. Additionally, on faded DIN schematics, the missing overline on the output can trick you into wiring a NOR gate as a standard OR gate, which will invert your expected logic and potentially short downstream enable lines.
Standard 14-Pin DIP Pinouts and IC Part Numbers
When you move from the schematic to the workbench, the NOR symbol translates into physical silicon. The most common physical package for hobbyists and repair technicians is the 14-pin Dual In-line Package (DIP) containing four independent 2-input NOR gates (a 'Quad 2-Input NOR').
Below are the most common ICs you will encounter, along with their voltage tolerances and propagation delays. Always check the datasheet for your specific suffix (e.g., SN74HC02N vs CD4001BE), as the logic family dictates your power supply requirements.
| Part Number | Logic Family | VCC Range | Typical Propagation Delay | Input Type |
|---|---|---|---|---|
| 74LS02 | Low-Power Schottky TTL | 4.75V – 5.25V | ~10 ns | Bipolar (Sources current) |
| 74HC02 | High-Speed CMOS | 2.0V – 6.0V | ~15 ns (at 5V) | CMOS (High impedance) |
| CD4001B | Standard CMOS (4000 series) | 3.0V – 15.0V | ~50 ns (at 10V) | CMOS (High impedance) |
The 7402 Pinout Trap
If you are used to wiring 7400 (NAND), 7408 (AND), or 7432 (OR) chips, you are accustomed to the standard pinout where inputs are on pins 1 and 2, and the output is on pin 3. The 7402 NOR gate breaks this rule.
On a standard 74xx02 IC, the outputs and inputs are reversed for the first and fourth gates to optimize internal silicon routing. According to the Texas Instruments SN74HC02 datasheet, the pinout is:
- Gate A: Output = Pin 1, Inputs = Pins 2 & 3
- Gate B: Inputs = Pins 5 & 6, Output = Pin 4
- Gate C: Inputs = Pins 8 & 9, Output = Pin 10
- Gate D: Output = Pin 13, Inputs = Pins 11 & 12
- GND: Pin 7 | VCC: Pin 14
Bench Tip: Wiring a 74HC02 using the standard 7432 OR-gate pinout will force you to feed your input signals into the chip's output drivers. This creates a direct bus contention, rapidly overheating the silicon and permanently bricking the IC. Always verify the pin 1 output orientation on NOR gates.
Identifying Unmarked or Faded NOR Gates on Legacy PCBs
When repairing industrial control boards or reverse-engineering legacy hardware, you will frequently encounter PCBs where the silkscreen has been baked off, or custom ASICs where the NOR symbol is entirely absent from the documentation. Safe interpretation requires a systematic approach to verify the logic function without relying on visual markings.
Step 1: Establish Power and Ground Reference
Before probing logic states, use a digital multimeter (DMM) in continuity mode to identify the ground plane. On standard 14-pin DIPs, Pin 7 is GND and Pin 14 is VCC. If the IC is unmarked, trace the pins to the nearest decoupling capacitor (usually 100nF); the capacitor's ground leg will confirm the GND pin. Never apply power or inject logic signals until VCC and GND are positively identified.
Step 2: Logic Probing the Truth Table
With the board powered at the correct nominal voltage (verify with a DMM first), use a logic probe or a microcontroller configured with pull-down resistors to test the suspected gate.
- Force all suspected inputs LOW. If the gate is a NOR, the output must read HIGH. (If it reads LOW, it may be an OR, AND, or NAND gate).
- Force any single input HIGH while keeping the others LOW. The output must immediately drop to LOW.
- Force all inputs HIGH. The output must remain LOW.
If the IC passes this sequence, you have empirically verified the NOR function, regardless of what the faded silkscreen says. For a deeper theoretical breakdown of how these states are achieved internally, refer to the All About Circuits NOR Gate tutorial.
Step 3: CMOS Die-Level and Schematic Tracing
If you are analyzing an unmarked schematic block or a decapsulated IC die under a microscope, you can identify a NOR gate by its internal transistor topology. In a standard 2-input CMOS NOR gate:
- The Pull-Down Network (NMOS) consists of two transistors in parallel. If either input goes HIGH, it creates a path to ground, pulling the output LOW.
- The Pull-Up Network (PMOS) consists of two transistors in series. Both inputs must be LOW to turn both PMOS transistors ON, creating a path to VCC and pulling the output HIGH.
Recognizing this parallel-NMOS / series-PMOS structure is the ultimate failsafe for identifying a NOR symbol when all external markings, standard references, and datasheets have failed.
