The Complete Inverter Gate Drive Truth Table
When designing or troubleshooting the power stage of a 48V DC-to-AC pure sine wave inverter, the inverter gate truth table is your foundational reference. It dictates the exact logic states required to drive the high-side and low-side switches (MOSFETs or IGBTs) in a full-bridge (H-bridge) topology without causing catastrophic shoot-through.
How to read this table: The table below maps the digital logic inputs from your microcontroller (PWM A and PWM B) to the physical switch states (Q1 through Q4) and the target Gate-to-Source voltage ($V_{GS}$). The base temperature rating for the Driver $I_{peak}$ Derating column is 25°C ambient. If your inverter enclosure runs hotter (e.g., 60°C+ in a solar charge path), you must apply the derating factor to your gate driver's peak output current to calculate actual switching speeds.
| State ID | Logic A (HIN) | Logic B (LIN) | Q1-Q4 Status (H-Bridge) | Target $V_{GS}$ (ON / OFF) | Dead-Time Insertion | Driver $I_{peak}$ Derating (@ 85°C) |
|---|---|---|---|---|---|---|
| 1 | HIGH | LOW | Q1 & Q4 ON Q2 & Q3 OFF |
+12V / 0V (Si) +15V / -4V (SiC) |
None (Steady State) | 0.75x Base Current |
| 2 | LOW | HIGH | Q2 & Q3 ON Q1 & Q4 OFF |
+12V / 0V (Si) +15V / -4V (SiC) |
None (Steady State) | 0.75x Base Current |
| 3 | LOW | LOW | All Switches OFF (Freewheeling) |
0V / 0V (Si) -4V / -4V (SiC) |
Mandatory (200ns - 500ns) | 0.75x Base Current |
| 4 | HIGH | HIGH | INVALID (Shoot-Through) | N/A | N/A (Hardware Interlock Required) | N/A |
| 5 | FAULT | FAULT | All Switches OFF (IEEE 1547 Anti-Islanding) |
0V (Discharged to GND) | Immediate Shutdown | 0A (Driver Disabled) |
Bookmark Quick-Jump: If you are debugging blown MOSFETs, jump straight to State 3 (Dead-Time). Insufficient dead-time between State 1 and State 2 is the number one cause of H-bridge failures on the bench.
Applying the Table to Your 48V Inverter Installation
A truth table on paper doesn't automatically translate to a working PCB. Here is how to map these rows to your physical 48V solar or UPS inverter build.
Which Column Applies to Your Installation?
It depends on your role in the build. If you are writing the firmware for the DSP or MCU (like a TI C2000 or STM32), the Logic A / Logic B columns are your primary concern; you are managing the PWM generation and hardware dead-time insertion. If you are designing the analog power stage and selecting the gate driver IC (e.g., a TI UCC21520 or Silicon Labs Si823x), the Target $V_{GS}$ and Driver $I_{peak}$ Derating columns dictate your component selection. You must ensure your driver's output voltage rails match the $V_{GS}$ requirements of your specific power transistors.
How Derating Rows Modify the Base Value
Gate driver ICs suffer from increased internal on-resistance ($R_{DS(on)}$) as junction temperatures rise. A typical 4A peak gate driver operating at a 25°C ambient base temperature will output exactly 4A. However, inside a sealed 48V inverter enclosure sitting in a hot garage, the ambient temperature can easily reach 60°C to 85°C.
Looking at the derating column, a factor of 0.75x at 85°C means your 4A driver is now only supplying 3A of peak current. This reduced current slows down the charging of the MOSFET's gate capacitance ($Q_g$), increasing your turn-on time ($t_{on}$) and drastically raising switching losses. If your thermal design doesn't account for this derating, the inverter will suffer from thermal runaway at high loads.
What the Table Cannot Tell You
The inverter gate truth table defines the ideal logic states, but it cannot account for parasitic loop inductance. If your PCB traces between the gate driver and the MOSFET gate are too long, the inductance will cause high-frequency ringing on the $V_{GS}$ waveform. This ringing can exceed the maximum $V_{GS}$ rating (usually ±20V) and punch through the gate oxide, destroying the transistor. Furthermore, the table cannot tell you the exact Miller plateau charge ($Q_{gd}$) of your specific MOSFET; you must consult the transistor's datasheet to calculate the required gate resistor ($R_g$) to dampen that ringing.
Inverter Gate Truth Table FAQ
How does dead-time in the gate truth table prevent shoot-through in H-bridges?
Dead-time (State 3) is a brief window where both the high-side and low-side switches on the same leg are held OFF. Because MOSFETs and IGBTs turn off slower than they turn on (due to the Miller effect and tail currents in IGBTs), sending a HIGH signal to Q1 at the exact same microsecond you send a LOW to Q2 will result in both being partially ON simultaneously. This creates a low-resistance path directly from the 48V DC bus to ground (shoot-through), resulting in massive current spikes that vaporize the silicon. Inserting 200ns to 500ns of dead-time ensures the outgoing switch is fully blocked before the incoming switch begins to conduct.
Why do SiC MOSFETs require negative gate voltage in the truth table?
If you are building a high-frequency inverter using wide-bandgap devices like Wolfspeed C3M series SiC MOSFETs, you will notice the table calls for a negative OFF-state voltage (e.g., -4V). Silicon MOSFETs have a relatively high gate threshold voltage ($V_{GS(th)}$ of 2V to 4V), making them immune to minor noise. SiC MOSFETs have a much lower threshold (often 1.5V to 2.5V). During high $dv/dt$ switching events, capacitive coupling through the Miller capacitance ($C_{gd}$) can induce a voltage spike on the gate that falsely turns the SiC device on. Applying a -4V bias during the OFF state provides a necessary noise margin to prevent this false turn-on.
What happens if the inverter gate logic signals overlap during state transitions?
If Logic A and Logic B are both HIGH (State 4), you command Q1 and Q2 (or Q3 and Q4) to turn on simultaneously. This is a dead short across your DC bus. In a 48V battery system capable of delivering 200A+ fault current, an overlap of just a few microseconds will cause the MOSFETs to explode, often taking the gate driver IC and the microcontroller's GPIO pins with it due to ground bounce. Always use gate drivers with built-in hardware anti-shoot-through (AST) or dead-time insertion logic to physically prevent State 4 from ever reaching the power stage, regardless of what the MCU commands.
How do I measure the physical gate voltage to verify the truth table states?
Never measure the gate drive of a high-side switch with a standard single-ended oscilloscope probe referenced to earth ground. The high-side MOSFET's source pin is floating at the switching node; connecting your scope's ground clip there will short the 48V DC bus directly to earth ground through the oscilloscope, destroying your probe and potentially the inverter. You must use a high-voltage differential probe (like the Tektronix THDP0200) or an isolated oscilloscope, placing the probe tips directly across the Gate and Source pins of the transistor as close to the package body as possible to avoid measuring trace inductance.
