Electrical Engineering Interview Questions Answers: PFC Sizing

Power factor correction (PFC) is the process of adding parallel capacitance to an inductive AC circuit to reduce the phase angle between voltage and current, thereby minimizing reactive power (kVAR) and maximizing real power (kW). When interviewers ask about this, they are testing your ability to bridge textbook phasor diagrams with physical hardware selection. In a real installation, correcting power factor changes the thermal limits of your infrastructure: it reduces line current, lowers $I^2R$ heating in conductors, avoids utility penalty tariffs, and frees up transformer kVA capacity for additional loads.

The most common confusion among junior engineers is mixing up displacement power factor (the phase shift caused by inductive loads like motors, which capacitors fix) with distortion power factor (the phase shift caused by non-linear loads like VFDs creating harmonics, which capacitors cannot fix and can actually make worse).

The Core Concept: Displacement vs. Distortion

To ace electrical engineering interview questions answers on this topic, you must immediately distinguish between displacement and distortion. Displacement power factor is governed by the fundamental 50/60Hz frequency. Inductive loads (transformers, induction motors, contactors) cause current to lag voltage. Capacitors cause current to lead voltage. By sizing the capacitor correctly, the leading and lagging reactive currents cancel out at the fundamental frequency.

Distortion power factor, however, is caused by high-frequency harmonics (3rd, 5th, 7th) generated by solid-state rectifiers and switching power supplies. If an interviewer asks, "Will adding capacitors fix the power factor of a facility full of LED drivers and VFDs?" the correct answer is: "No, it will only fix the displacement component, and it risks creating a dangerous parallel resonance with the harmonic frequencies." For distortion, you need active harmonic filters or multi-pulse transformers, not passive capacitors.

The Numeric Proof: Sizing a PFC Capacitor Bank

Interviewers will almost always hand you a calculator and a scenario. Here is the exact framework to solve it without hesitation.

The Scenario: You have a 50 kW industrial air compressor motor running at an existing power factor of 0.75. The utility mandates a target power factor of 0.95. What size capacitor bank (in kVAR) do you specify?

Step 1: Find the initial and target phase angles.

• $\theta_1 = \arccos(0.75) = 41.41^\circ$
• $\theta_2 = \arccos(0.95) = 18.19^\circ$

Step 2: Calculate the tangent of both angles.

• $\tan(41.41^\circ) = 0.8819$
• $\tan(18.19^\circ) = 0.3287$

Step 3: Apply the kVAR formula.

$Q_c = P \times (\tan\theta_1 - \tan\theta_2)$
$Q_c = 50 \times (0.8819 - 0.3287)$
$Q_c = 50 \times 0.5532 = 27.66 \text{ kVAR}$

Step 4: Select the standard hardware size.
Capacitors are manufactured in standard steps (e.g., 5, 10, 15, 20, 25, 30 kVAR). You never want to overcorrect into a leading power factor, which can cause voltage instability. However, since 27.66 is very close to 30, and accounting for typical capacitor tolerance (-5% to +10%), you would specify a 30 kVAR bank but ensure the controller has a C/K ratio setting that prevents switching the final stage unless absolutely necessary, or select a custom 25 kVAR + 5 kVAR switched bank.

Where You Meet This in Practice

You will encounter PFC hardware in three primary environments:

1. Motor Control Centers (MCCs): Localized, fixed capacitors wired directly across the line-side of a motor starter contactor. They switch on and off with the motor.
2. Main Distribution Boards (MDBs): Centralized, automatic switched capacitor banks (often 100 to 400 kVAR) monitored by a microprocessor relay that reads the main incoming CT (Current Transformer) and switches stages in/out to maintain a facility-wide target.
3. Utility Metering Cabinets: Where the revenue meter sits. If the facility PF drops below 0.90, utilities apply a multiplier to the demand charge. PFC here directly impacts the monthly OPEX.

Decision Tree: Choosing the Right PFC Hardware

When an interviewer asks, "How do you select the equipment?" use this exact decision matrix. Do not give a vague 'it depends' answer; terminate the logic in a concrete hardware pick.

The Resonance Trap: Harmonics and Detuning

This is the ultimate separator between junior and senior candidates. If you add pure capacitance to a grid that has harmonic currents, you create a parallel LC circuit. The resonant frequency is calculated as $f_r = \frac{1}{2\pi\sqrt{LC}}$.

If that resonant frequency happens to land on the 5th harmonic (300Hz in a 60Hz system) or 7th harmonic (420Hz), the impedance at that frequency shoots to infinity. The result? Massive harmonic voltage amplification, blown capacitor fuses, melted busbars, and tripped upstream breakers.

For deeper reading on utility-side impacts, the US Department of Energy's Advanced Manufacturing Office provides excellent baseline data on how poor power factor degrades national grid efficiency. For the foundational math behind the phasor relationships, All About Circuits offers a rigorous breakdown of the AC power triangle.

FAQ: Quick-Fire Interview Answers

When faced with power factor questions, default to the 0.95 target, calculate the exact kVAR using the tangent method, and always check the harmonic profile before specifying standard capacitors over detuned reactor banks.