Consensus Law Boolean Algebra: Simplify Logic and Eliminate Hazards

The consensus law in Boolean algebra states that in an expression containing a variable, its complement, and a third term formed by the remaining variables, that third term is redundant and can be eliminated without changing the logic output. When designing digital logic—whether you are wiring discrete 7400-series ICs on a bench, writing ladder logic for an Allen-Bradley PLC, or synthesizing Verilog for an AMD/Xilinx FPGA—redundant terms waste physical board space, increase propagation delay, and draw excess quiescent current. However, as we will cover later, intentionally adding this "redundant" term is a critical technique for preventing race conditions in high-speed circuits.

The Core Mechanism: How the Consensus Theorem Works

The standard sum-of-products (SOP) form of the consensus theorem is written as:

XY + X'Z + YZ = XY + X'Z

In this equation, YZ is the consensus term. It is generated by multiplying the two non-complemented variables from the other two terms (Y from the first term, Z from the second). Because the first two terms already cover all possible states of X (X is either 1 or 0), the YZ term adds no new logical conditions to the final output. If X is 1, the XY term dictates the output. If X is 0, the X'Z term dictates the output. The YZ term is mathematically shadowed by the other two.

The theorem also has a dual form used for product-of-sums (POS) expressions:

(X + Y)(X' + Z)(Y + Z) = (X + Y)(X' + Z)

Here, (Y + Z) is the redundant consensus term. According to standard Boolean rules documented by All About Circuits, recognizing both forms allows you to simplify complex logic arrays before you ever touch a schematic capture tool.

Worked Example: Gate Reduction in a Safety Interlock

Let’s look at a real-world scenario: designing a safety interlock for an industrial stamping press using discrete logic ICs. We have three inputs:

• X: Press Cycle Active
• Y: Light Curtain Clear
• Z: Manual Override Engaged

The original logic equation derived from the truth table is:

F = XY + X'Z + YZ

Original Circuit Implementation:

1. AND Gate 1: X · Y
2. AND Gate 2: X' · Z (Requires an inverter for X')
3. AND Gate 3: Y · Z
4. OR Gate 1: Combines (X · Y) and (X' · Z)
5. OR Gate 2: Combines the output of OR Gate 1 with (Y · Z)

The Reduction:

By identifying YZ as the consensus term, we eliminate it. The simplified equation is F = XY + X'Z.

Quantifiable Savings:

By dropping the consensus term, we eliminate an entire cascaded OR stage. In high-speed digital design, saving 14ns of propagation delay can be the difference between a stable 50MHz clock domain and a failing timing closure. For a deeper look at how these laws map to physical gates, Electronics Tutorials provides excellent schematic breakdowns of Boolean simplifications.

Where You Meet This in Practice (And the Hazard Gotcha)

You will encounter the consensus law in three primary areas of electrical and electronic engineering:

1. PLC Ladder Logic Optimization

When writing Function Block Diagrams (FBD) or ladder logic for a Siemens or Allen-Bradley PLC, the compiler automatically applies consensus reduction. However, if you are troubleshooting a legacy machine and see a seemingly redundant rung of contacts (e.g., a parallel branch that mimics the YZ term), you now know it is logically redundant and can be safely removed to reduce scan time.

2. FPGA Synthesis and RTL Design

Tools like AMD Vivado or Intel Quartus aggressively minimize logic using consensus and other Karnaugh-map derivations. When you view the synthesized RTL schematic, you will notice the consensus terms are gone, replaced by optimized Look-Up Tables (LUTs).

3. The Hazard Gotcha: When to ADD the Consensus Term

This is where textbook theory diverges from bench reality. While the consensus law says you can remove the YZ term, practicing digital design engineers sometimes intentionally add it to eliminate static-1 hazards.

Imagine X transitioning from 1 to 0. The physical inverter generating X' has a propagation delay (e.g., 5ns). During that 5ns window, both X and X' are momentarily 0. If Y=1 and Z=1, the terms XY and X'Z both drop to 0, causing the output F to glitch to 0 for 5ns before X' goes high and restores the output to 1.

If that output F is connected to a clock enable or an asynchronous reset line, that 5ns glitch will cause catastrophic system failure. By intentionally adding the consensus term (YZ), you create a third logical path that remains high (1·1 = 1) during the inverter's propagation delay, effectively masking the glitch. This technique is detailed in advanced digital logic design resources covering hazard elimination.

Common Confusions: Consensus vs. Absorption

The most frequent mistake students and junior technicians make is confusing the consensus law with the absorption law.

• Absorption Law: A + AB = A. This relies on a term being a subset of another term. It does not require a complemented variable.
• Consensus Law: XY + X'Z + YZ = XY + X'Z. This strictly requires a variable (X) and its exact complement (X') to be present in the first two terms.

If you look at an equation like A + A'B + AB, do not try to apply consensus. Instead, factor it: A + AB + A'B simplifies via absorption to A + A'B, which further simplifies via a different Boolean rule to A + B. Always look for the distinct complemented pair (X and X') before attempting to strike out a consensus term.